Joachim C. Reiner

Electrostatic discharge directly to the chip surface, caused by automatic post-wafer processing

Up to now, ESD damage is understood to be induced via device pads and to be avoided by means of appropriate protection structures located at these pads. The ESD susceptibility is classified by means of standardized stress tests. This paper shows, that with increasing importance a variety of post-wafer manufacturing and packaging processes may create a new type of evident and latent ESD damage in the device. We define this phenomenon as ESD-from-outside-to-surface (ESDFOS), as charged handlers cause discharges directly from outside into the device surface. Classical ESD tests do not cover this mechanism. The paper describes the phenomenon, its root causes, and gives practical hints for analysis and prevention.

Pseudo-progressive breakdown of ultra-thin nitrided gate oxide

The breakdown behaviour of n-MOSTs with nitrided ultra-thin gate oxide of about 1.6 nm effective oxide thickness (EOT) has been investigated. The leakage current versus time curves show a combination of spontaneous and successive breakdown, as well as multiple breakdown events on the same sample. The paper shows the phenomenon and discusses the implications for a proper selection of failure criteria for reliability assessment. Statistics of breakdown occurrence times yield more consistent data than that based on time to leakage current criterion.

A systematic leakage current analysis of gate oxide soft breakdown

Soft breakdown is a breakdown mechanism observed for gate oxide layer thickness of 7 nm and less. The physical origin of this new reliability issue is still under debate. The results presented here show that most of the preand post-breakdown leakage current phenomena can be observed on the same sample. This indicates that the breakdown of a thin gate oxide is a complex process. The leakage current bursts observed before the (soft) breakdown event might be used as pre-breakdown trigger signal possibly allowing the study of the weak spot before its destruction by the breakdown event.

Reversible leakage current switching in thin gate oxides - soft breakdown or noise? [MOSFETs]

In this study, p-MOSFETs with 3.5 nm gate oxide thickness are stressed electrically in inversion mode. Next to the better known random leakage current fluctuations such as bursts, pronounced reversible switching or RTS behaviour has been observed in these devices. The cause of reversible switching must be qualitatively different from irreversible breakdown phenomena such as soft or hard breakdown. Positively charged traps within the oxide layer, which can switch from neutral to positive by trapping or de-trapping of an electron into or out of a deep state, are proposed as the cause for reversible, pre-breakdown leakage current switching.

Similarity of pre-breakdown leakage current fluctuations of p- and n-MOSFETs

In the presented study, p- and n- MOSFETSs with 5nm gate oxide thickness are stressed electrically in inversion mode. Pre-breakdown leakage current fluctuations, as switching and RTS behaviour and bursts, occur quite similarly for both kinds of devices. Positively charged traps within the oxide layer, which can switch from neutral to positive by trapping or de-trapping of an electron into or out of a deep state, are proposed as a cause for pre-breakdown leakage current switching RTS behaviour for both p- and n-MOSFET devices.