Peter Jacob

Reliability and wearout characterisation of LEDs

Abstract LEDs play a key role as an active element in electronic circuitry – for example in optocouplers. Their life time strongly depends on the operation conditions. Degradation usually starts by the generation of both reverse and forward bias direction pinpoint leakage paths. When the resistance of such a path becomes lower than the regular operational resistance in forward direction, it will start to act as a bypass. Then, reduced and inhomogeneous emission is the first degradation indicator. The paper describes degradation mechanisms and their characterisation.

Electrostatic discharge directly to the chip surface, caused by automatic post-wafer processing

Up to now, ESD damage is understood to be induced via device pads and to be avoided by means of appropriate protection structures located at these pads. The ESD susceptibility is classified by means of standardized stress tests. This paper shows, that with increasing importance a variety of post-wafer manufacturing and packaging processes may create a new type of evident and latent ESD damage in the device. We define this phenomenon as ESD-from-outside-to-surface (ESDFOS), as charged handlers cause discharges directly from outside into the device surface. Classical ESD tests do not cover this mechanism. The paper describes the phenomenon, its root causes, and gives practical hints for analysis and prevention.

Failure causes generating aluminium protrusion/extrusion

Abstract Aluminium protrusion/extrusion are frequent failures, which are responsible for severe short damage in semiconductor devices. Unfortunately, the mechanisms results also frequently as an artifact of many other high-current failure signatures as EOS, which makes root cause investigations sometimes rather difficult. To overcome the problem, most frequent root causes for aluminium protrusion/extrusion are shown and discussed in this paper. This information combined with the individual device process- and testing history helps to conclude to the failure root cause. The authors evaluated and reviewed related case studies of their own practice resulting in following root causes for aluminium protrusions and extrusions: laser-induced damage, ESDFOS, application-related EOS, thermal cycling, thermomechanical mismatch in stacked devices, ultrasonic-induced damaging, micro-Si-particles in chip-pick&place and surface-pressure-induced damage, as for instance when doing copper-wirebonding.

Device decapsulated (and/or depassivated) – Retest ok – What happened?

Abstract One of the very first steps to enter into physical device failure analysis is the device decapsulation. In some cases, an additional depassivation follows to give access to contact needles for internal probing. However, it happens from time-to-time that the device has been cured from its failure behaviour. Such cases often end as non-conclusive analysis result. Our principle investigations and results, however, will help to understand the mechanisms and allow in many “hopeless” cases to draw useful conclusions on the root causes. These are linked in most cases to metal related failures. Besides the “classical case” of touching bond wires, typical root causes are metal filament shorts in the nanometer-order-of magnitude, which can be removed easily by mechanical and/or chemical effects of any delayering procedure. Surface metal shorts may also be generated by bump metal or pad-interface-metallisation-redeposition onto the passivation surface and by metal residue-related recombinations of trimming fuses. In both latter cases, nanometer metal films short-circuit neighbouring pads or fuses in trimming-fuse-arrays. This paper describes these and some second-order mechanisms in detail, which sometimes let the chip recover after decapsulation and/or depassivation.

New ESD challenges in RFID manufacturing

Abstract The introduction of dual-band RFIDs (Radio Frequency Identification Devices) in chip cards created new ESD risks with unconventional discharge paths. On a plastic foil, a more or less grounded coil antenna for radio frequency (RF) is aluminium-printed on one half of the card. On the other half, an electrical floating, but thus, highly electrostatic charged folded dipole for ultrahigh frequency (UHF) is arranged. When the chip is placed by a flip-chip assembly process, a strong discharge takes place through the RF-UHF-path of the chip. Usual ESD protective structures are only of limited use in these cases. Discharge paths and specific risks are described in this paper as well as useful countermeasures in foil and assembly processes.

Unusual defects, generated by wafer sawing: An update, including pick&place processing

Abstract At ESREF 2008, the paper “Unusual defects, generated by wafer sawing: Diagnosis, mechanisms and how to distinguish from related failures” had won the Best Paper Award. In the meantime, new experiences were collected, related to new methods as laser sawing and its specific ESD risks and additional failure mechanisms as backside damage, charging of foils, pad corrosion and sawing residue damages . This paper explains in detail these failure sources, including detailed explanations on root causes and physical mechanisms as well as important hints for failure analysts how to distinguish related failure signatures from those, which look similar but are of other origin.

Reading distance degradation mechanisms of near-field RFID devices.

In case of operation distance degradation, frequently RFID chips are extracted from their tags and electrically/physically analysed. However, manifold mechanisms based on interaction effects between package and device, exist. This paper examines and highlights these mechanisms, giving also valuable hints for the failure analyst.

Wire-ball-bonding process evaluatiuon by using focused ion beam bondball characterization

The adjustment of bonding parameters has been based for long time exclusively on the results of pull- and shear tests. Observing these parameters to be too low, bondparameters have been usually adjusted towards a stronger direction. FIB characterization, however, has shown, that in many cases pull forces have been at a low level, because the top chip metal layer (aluminum) has been completely consumed by the bondball- gold, forming a thick intermetallic phase with only weak adhesion to the barrier layer or intermetal dielectric. In these cases, reduction of the bonding parameters would be the suitable corrective action, whilst stronger adjustment results in cracking the silicon device or local cratering. Using different adjustments of bonding parameters, the point of optimum could be well found, corrected by the results of FIB- cross-sectional characterization. A good corresponding between cross-section analysis results and bonding process parameters has been found. It gives valuable hints on both process- homogeneity over the whole bonding length as well as on the optimum of the intermetallic layer thickness, which still should leave a continuous layer of chip metal. The border extremes show at one end of the process window local weak bonding and delamination lines, at the other end a completely consumed chip metallization. FIB characterization shows the bonding process influence on the grain structure of both wire and chip metallization, too.

Design and reliability aspects of multilevel metal large-scale power line layouts in ULSI-ICs

Integration of both extremely small-dimensioned metal lines and large-dimensioned metal structures may cause reliability problems due to thermomechanical stress between the intermetal dielectric and the multi-level-metalization. The paper reports a case study and shows a problem solution approach: due to thermomechanical mismatch of aluminum and Si-oxide, metalization processing should not be used for both small and large structures. This may cause cracks and generate intermetallic shorts as a reliability problem.

Identification of amorphous silicon residues in a low-power CMOS technology

A large variety of physical analysis techniques are used in the semiconductor industry to identify defects impacting yield or reliability. Identification of a defect often requires the combined use of several techniques to give a clear understanding of the defect nature. In the present study, several microscopy techniques (SEM, TEM, Analytical-TEM, AFM and FIB) have been intensively used to identify the origin of residues observed on the edge of large active areas in a low power CMOS technology. A KLA automatic inspection system has been used for locating and quantifying the defects. It has been shown that the defects are related to amorphous silicon residues whose origin is related to the gate deposition process. In the process, the polysilicon gate is deposited in two steps. A first thin amorphous silicon layer is deposited, through which the Vt implant is done, followed by the deposition of a thick polysilicon layer. Analysis of defaults showed that the residues are related to a non-uniform thin oxide layer located between the thick polysilicon layer and the underlying thin amorphous silicon, which halts the polysilicon gate etch. Thicker native oxide on amorphous silicon due to humidity or drying spots is the presumed source of the thin non-uniform oxide. Increasing the HF dip before the polysilicon deposition eliminated almost all residues. No negative effect on the oxide quality or other electrical parameter has been observed. Eliminating altogether the amorphous-Si gate deposition process is an even more robust solution.