Joachim Knoch

High-performance carbon nanotube field-effect transistor with tunable polarities

State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky-barrier-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance enhancement-mode CNFETs exhibiting n- or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S=63 mV/dec). The device design allows for aggressive oxide thickness and gate-length scaling while maintaining the desired device characteristics.

Toward Nanowire Electronics

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

Donor deactivation in silicon nanostructures

The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.

Modeling of High-Performance p-Type III–V Heterojunction Tunnel FETs

The impact of band lineup and source doping concentration on the performance of heterojunction tunnel FETs (H-TFETs) with type-II heterointerface is investigated by simulations. Exemplarily, H-TFETs based on InAs/AlxGa1-xSb heterostructures are studied. Varying the Al content x, the band lineup can be adjusted from staggered to broken. We find that a staggered band lineup and a medium source doping concentration yield the best ON/OFF-state performance in terms of an inverse subthreshold slope that is smaller than 60 mV/dec and fT values in the terahertz range.

Silicon nanowire tunneling field-effect transistors

We demonstrate the implementation of tunneling field-effect transistors (TFETs) based on silicon nanowires (NWs) that were grown using the vapor-liquid-solid growth method. The Si NWs contain p-i-n+ segments that were achieved by in situ doping using phosphine and diborane as the n- and p-type dopant source, respectively. Electrical measurements of the TFETs show a band-to-band tunneling branch in the transfer characteristics. Furthermore, an increase in the on-state current and a decrease in the inverse subthreshold slope upon reducing the gate oxide thickness are measured. This matches theoretical calculations using a Wenzel Kramer Brillouin approximation with nanowire diameter and oxide thickness as input parameters.

Carbon nanotube electronics

Presents experimental results on single-wall carbon nanotube field-effect transistors (CNFETs) operating at gate and drain voltages below 1V. Taking into account the extremely small diameter of the semiconducting tubes used as active components, electrical characteristics are comparable with state-of-the-art metal oxide semiconductor field-effect transistors (MOSFETs). While output as well as subthreshold characteristics resemble those of conventional MOSFETs, we find that CNFET operation is actually controlled by Schottky barriers (SBs) in the source and drain region instead of by the nanotube itself. Due to the small size of the contact region between the electrode and the nanotube, these barriers can be extremely thin, enabling good performance of SB-CNFETs.

High performance of potassium n-doped carbon nanotube field-effect transistors

We describe a robust technique for the fabrication of high performance vertically scaled n-doped field-effect transistors from large band gap carbon nanotubes. These devices have a tunable threshold voltage in the technologically relevant range (−1.3 V⩽Vth⩽0.5 V) and can carry up to 5–6 μA of current in the on-state. We achieve such performance by exposure to potassium (K) vapor and device annealing in high vacuum. The treatment has a twofold effect to: (i) controllably shift Vth toward negative gate biases via bulk doping of the nanotube (up to about 0.6e−/nm), and (ii) increase the on-current by 1–2 orders of magnitude. This current enhancement is achieved by lowering external device resistance due to more intimate contact between K metal and doped nanotube channel in addition to potential reduction of the Schottky barrier height at the contact.

Impact of the channel thickness on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors

We present quantum simulations of single-gated Schottky barrier metal–oxide–semiconductor field-effect transistors on ultrathin silicon on insulator. The electrostatics of such devices is investigated and the influence of the silicon thickness on the Schottky barriers at the source and drain and, thus, the influence on the current–voltage characteristics are elaborated. We show that decreasing the channel layer thickness leads to a strong reduction of the Schottky barrier thickness and thus to an increased gate control of the drain current. The use of ultrathin channel layers improves the off- as well as the on state of such transistors and results in electrical characteristics comparable with conventional metal–oxide–semiconductor field-effect transistors.

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage Vth of SOI SB-MOSFETs and find a nonmonotonic behavior of Vth. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be ~ 3 nm

Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs

The effect of dopant segregation (DS) on the electrical behavior of silicon-on-insulator Schottky barrier MOSFETs (SB-MOSFETs) is investigated. Ion implantation with arsenic and boron and subsequent silicidation is used to create highly n- and p-doped interface layers at the silicide-silicon interface. As a result, a strong band bending occurs at the silicide-silicon interface giving rise to a lowering of the effective Schottky barrier height. In turn, an increased electron as well as hole injection into the channel leads to improvements of the off- and on-state of the SB-MOSFETs. Using dopant segregation n-type as well as p-type SB-MOSFETs with nickel silicide source/drain electrodes have been fabricated exhibiting an inverse sub-threshold slope close to the thermal limit and showing one order of magnitude higher on-currents if compared to SB-MOSFETs without DS. In essence, the use of dopant segregation allows the fabrication of high performance Schottky barrier MOSFETs.