João P. Marques Silva

Prime implicant computation using satisfiability algorithms

The computation of prime implicants has several and significant applications in different areas, including automated reasoning, non-monotonic reasoning, electronic design automation, among others. The authors describe a new model and algorithm for computing minimum-size prime implicants of propositional formulas. The proposed approach is based on creating an integer linear program (ILP) formulation for computing the minimum-size prime implicant, which simplifies existing formulations. In addition, they introduce two new algorithms for solving ILPs, both of which are built on top of an algorithm for propositional satisfiability (SAT). Given the organization of the proposed SAT algorithm, the resulting ILP procedures implement powerful search pruning techniques, including a non-chronological backtracking search strategy, clause recording procedures and identification of necessary assignments. Experimental results, obtained on several benchmark examples, indicate that the proposed model and algorithms are significantly more efficient than other existing solutions.

Dynamic Search-Space Pruning Techniques in Path Sensitization

A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path sensitization can be posed as a search, in the n-dimensional Boolean space, for a consistent assignment of logic values to the circuit nodes which also satisfies a given condition. In this paper we propose and demonstrate the effectiveness of several new techniques for search-space pruning for test pattern generation. In particular, we present linear-time algorithms for dynamically identifying unique sensitization points and for dynamically maintaining reduced head line sets. In addition, we present two powerful mechanisms that drastically reduce the number of backtracks: failure-driven assertions and dependency-directed backtracking. Both mechanisms can be viewed as a form of learning while searching and have analogs in other application domains. These search pruning methods have been implemented in a generic path sensitization engine called LEAP. A test pattern generator, TG-LEAP, that uses this engine was also developed. We present experimental results that compare the effectiveness of our proposed search pruning strategies to those of PODEM, FAN, and SOCRATES. In particular, we show that LEAP is very efficient in identifying undetectable faults and in generating tests for difficult faults.

Efficient Algorithms for the Inference of Minimum Size DFAs

This work describes algorithms for the inference of minimum size deterministic automata consistent with a labeled training set. The algorithms presented represent the state of the art for this problem, known to be computationally very hard.In particular, we analyze the performance of algorithms that use implicit enumeration of solutions and algorithms that perform explicit search but incorporate a set of techniques known as dependency directed backtracking to prune the search tree effectively.We present empirical results that show the comparative efficiency of the methods studied and discuss alternative approaches to this problem, evaluating their advantages and drawbacks.

Efficient and robust test generation-based timing analysis

This paper describes a new path sensitization model in which search-space pruning techniques commonly used in test pattern generation can be applied to timing analysis. A safe static sensitization criterion, equivalent to floating-mode sensitization, is proposed and represented in the new path sensitization model. This model has been used to implement a timing analysis tool, TA-LEAP, and preliminary results indicate significant performance gains over previous methods.<<ETX>>

Timing analysis using propositional satisfiability

The existence of false paths represents a significant and computationally complex problem in the timing analysis of combinational and sequential circuits. In this paper we describe propositional satisfiability based algorithms for timing analysis, which introduce significant perfomance improvements over existing procedures. In particular we address the problems of circuit delay computation and path delay validation, describing algorithms and providing experimental results for both problems.

Efficient search techniques for the inference of minimum size finite automata

We propose a new algorithm for the inference of the minimum size deterministic automaton consistent with a prespecified set of input/output strings. Our approach improves a well known search algorithm proposed by A.W. Bierman and J.A. Feldman (1972), by incorporating a set of techniques known as dependency directed backtracking. These techniques have already been used in other applications, but we are the first to apply them to this problem. The results show that the application of these techniques yields an algorithm that is, for the problems studied, orders of magnitude faster than existing approaches.

An analysis of path sensitization criteria

We introduce a new framework for describing path sensitization criteria in combinational networks. This framework is used to analyze and categorize several sensitization criteria proposed in the past. We discuss some misconceptions of existing sensitization criteria, and evaluate the effects of hazards on the delay of combinational circuits. Finally, we introduce a new sensitization criterion representing a lower bound on the delay of the longest sensitizable path.<<ETX>>

FPD-an environment for exact timing analysis

The authors introduce a novel circuit model that accurately represents the temporal behavior of combinational circuits. This circuit model is the basis for the derivation of a new sensitizing criterion which provides the necessary conditions for accurate timing analysis. The authors describe the FPD timing analysis environment supported by the sensitizing criterion and present examples of its application.<<ETX>>

Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation

Ravel-XL is a single-board hardware accelerator for gate-level digital logic simulation. It uses a standard levelized-code approach to statically schedule gate evaluations. However, unlike previous approaches based on levelized-code scheduling, it is not limited to zero- or unit-delay gate models and can provide timing accuracy comparable to that obtained from event-driven methods. We review the synchronous waveform algebra that forms the basis of the Ravel-XL simulation algorithm, present an architecture for its hardware realization, and describe an implementation of this architecture as a single VLSI chip. The chip has about 900000 transistors on a die that is approximately 1.4 cm/sup 2/, requires a 256 pin package and is designed to run at 33 MHz. A Ravel-XL board consisting of the processor chip and local instruction and data memory can simulate up to one billion gates at a rate of approximately 6.6 million gate evaluations per second. To better appreciate the tradeoffs made in designing Ravel-XL, we compare its capabilities to those of other commercial and research software simulators and hardware accelerators.

Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation

Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT ”packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks.