Karem A. Sakallah

Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints

Much research in the area of constraint processing has recently been focused on extracting small unsatisfiable “cores” from unsatisfiable constraint systems with the goal of finding minimal unsatisfiable subsets (MUSes). While most techniques have provided ways to find an approximation of an MUS (not necessarily minimal), we have developed a sound and complete algorithm for producing all MUSes of an unsatisfiable constraint system. In this paper, we describe a relationship between satisfiable and unsatisfiable subsets of constraints that we subsequently use as the foundation for MUS extraction algorithms, implemented for Boolean satisfiability constraints. The algorithms provide a framework with which many related subproblems can be solved, including relaxations of completeness to handle intractable instances, and we develop several variations of the basic algorithms to illustrate this. Experimental results demonstrate the performance of our algorithms, showing how the base algorithms run quickly on many instances, while the variations are valuable for producing results on instances whose complete results are intractably large. Furthermore, our algorithms are shown to perform better than the existing algorithms for solving either of the two distinct phases of our approach.

SATIRE: a new incremental satisfiability engine

We introduce SATIRE, a new satisfiability solver that is particularly suited to verification and optimization problems in electronic design automation. SATIRE builds on the most recent advances in satisfiability research, and includes two new features to achieve even higher performance: a facility for incrementally solving sets of related problems, and the ability to handle non-CNF constraints. We provide experimental evidence showing the effectiveness of these additions to classical satisfiability solvers.

Theory and Applications of Satisfiability Testing (SAT 2007)

SAT: Past and Future.- Encodings of Problems in Effectively Propositional Logic.- Efficient Circuit to CNF Conversion.- Mapping CSP into Many-Valued SAT.- Circuit Based Encoding of CNF Formula.- Breaking Symmetries in SAT Matrix Models.- Partial Max-SAT Solvers with Clause Learning.- MiniMaxSat: A New Weighted Max-SAT Solver.- Solving Multi-objective Pseudo-Boolean Problems.- Improved Lower Bounds for Tree-Like Resolution over Linear Inequalities.- Horn Upper Bounds and Renaming.- Matched Formulas and Backdoor Sets.- Short XORs for Model Counting: From Theory to Practice.- Variable Dependency in Local Search: Prevention Is Better Than Cure.- Combining Adaptive Noise and Look-Ahead in Local Search for SAT.- From Idempotent Generalized Boolean Assignments to Multi-bit Search.- Satisfiability with Exponential Families.- Formalizing Dangerous SAT Encodings.- Algorithms for Variable-Weighted 2-SAT and Dual Problems.- On the Boolean Connectivity Problem for Horn Relations.- A First Step Towards a Unified Proof Checker for QBF.- Dynamically Partitioning for Solving QBF.- Backdoor Sets of Quantified Boolean Formulas.- Bounded Universal Expansion for Preprocessing QBF.- Effective Incorporation of Double Look-Ahead Procedures.- Applying Logic Synthesis for Speeding Up SAT.- Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver.- A Lightweight Component Caching Scheme for Satisfiability Solvers.- Minimum 2CNF Resolution Refutations in Polynomial Time.- Polynomial Time SAT Decision for Complementation-Invariant Clause-Sets, and Sign-non-Singular Matrices.- Verifying Propositional Unsatisfiability: Pitfalls to Avoid.- A Simple and Flexible Way of Computing Small Unsatisfiable Cores in SAT Modulo Theories.- SAT Solving for Termination Analysis with Polynomial Interpretations.- Fault Localization and Correction with QBF.- Sensor Deployment for Failure Diagnosis in Networked Aerial Robots: A Satisfiability-Based Approach.- Inversion Attacks on Secure Hash Functions Using sat Solvers.

Congestion driven quadratic placement

This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The interplay between routing analysis and quadratic placement using growth matrix permits global treatment of congestion. Further reduction in congestion is obtained by the relaxation of pin constraints. Experiments show improvements in wireability.

Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT

1. ABSTRACT lier BDD-based methods. Boolean-based routing transforms the geometric FPGA routing task into a single, large Boolean equation with the property that any assignment of input variables that “satisfies” the equation (that renders equation identically “1”) specifies a valid routing. The formulation has the virtue that it considers all nets simultaneously, and the absence of a satisfying assignment implies that the layout is unroutable. Initial Boolean-based approaches to routing used Binary Decision Diagrams (BDDs) to represent and solve the layout problem. BDDs, however, limit the size and complexity of the FPGAs that can be routed, leading these approaches to concentrate only on individual FPGA channels. In this paper, we present a new search-based Satisfiability (SAT) formulation that can handle entire FPGAs, routing all nets concurrently. The approach relies on a recently developed SAT engine (GRASP) that uses systematic search with conflict-directed non-chronological backtracking, capable of handling very large SAT instances. We present the first comparisons of search-based SAT routing results to other routers, and offer the first evidence that SAT methods can actually demonstrate the unroutability of a layout. Preliminary experimental results suggest that this approach to FPGA routing is more viable than ear1.1

Solving difficult SAT instances in the presence of symmetry

Research in algorithms for Boolean satisfiability and their implementations [23, 6] has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks [10] can be solved in seconds on commodity PCs. More recent benchmarks take longer to solve because of their large size, but are still solved in minutes [25]. Yet, small and difficult SAT instances must exist because Boolean satisfiability is NP-complete.We propose an improved construction of symmetry-breaking clauses [9] and apply it to achieve significant speed-ups over current state-of-the-art in Boolean satisfiability. Our techniques are formulated as pre-processing and can be applied to any SAT solver without changing its source code. We also show that considerations of symmetry may lead to more efficient reductions to SAT in the routing domain.Our work articulates SAT instances that are unusually difficult for their size, including satisfiable instances derived from routing problems. Using an efficient implementation to solve the graph automorphism problem [18, 20, 22], we show that in structured SAT instances difficulty may be associated with large numbers of symmetries.

Robust search algorithms for test pattern generation

In recent years several highly effective algorithms have been proposed for Automatic Test Pattern Generation (ATPG). Nevertheless, most of these algorithms too often rely on different types of heuristics to achieve good empirical performance. Moreover there has not been significant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heuristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algorithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfiability (SAT) algorithm, the same concepts can be integrated on application-specific algorithms.

Robust SAT-Based Search Algorithm for Leakage Power Reduction

Leakage current promises to be a major contributor to power dissipation in future technologies. Bounding the maximum and minimum leakage current poses an important problem. Determining the maximum leakage ensures that the chip meets power dissipation constraints. Applying an input pattern that minimizes leakage allows extending battery life when the circuit is in standby mode. Finding such vectors can be expressed as a satisfiability problem. We apply in this paper an incremental SAT solver, PBS [1], to find the minimum or maximum leakage current. The solver is called as a post-process to a random-vector-generation approach. Our results indicate that using a such a generic SAT solver can improve on previously proposed random approaches [7].

Boolean satisfiability in electronic design automation

Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks.

Improved Design Debugging Using Maximum Satisfiability

In todays SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sources in designs automatically. Unfortunately, the capacity and performance of such automated techniques must be considerably extended for industrial applicability. This work aims to improve the performance of current state-of-the-art debugging techniques, thus making them more practical. More specifically, this work proposes a novel design debugging formulation based on maximum satisfiability (max-sat) and approximate max-sat. The developed technique can quickly discard many potential error sources in designs, thus drastically reducing the size of the problem passed to an existing debugger. The max-sat formulation is used as a pre-processing step to construct a highly optimized debugging framework. Empirical results demonstrate the effectiveness of the proposed framework as run-time improvements of orders of magnitude are consistently realized over a state-of-the-art debugger.