Johann Laurent

Functional level power analysis: an efficient approach for modeling the power consumption of complex processors

A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePowers approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.

Power consumption modeling and characterization of the TI C6201

This new approach characterizes power dissipation on complex dsps. its processor model relies on an initial functional-level power analysis of the target processor together with a characterization that qualifies the more significant architectural and algorithmic parameters for power dissipation. these parameters come from a simple profiling of the assembly code. This functional model accounts for deeply pipelined, superscalar, and hierarchical memory architectures.

Softexplorer: estimating and optimizing the power and energy consumption of a C program for DSP applications

We present a method to estimate the power and energy consumption of an algorithm directly from the C program. Three models are involved: a model for the targeted processor (the power model), a model for the algorithm, and a model for the compiler (the prediction model). A functional-level power analysis is performed to obtain the power model. Five power models have been developed so far, for different architectures, from the simple RISC ARM7 to the very complex VLIW DSP TI C64. Important phenomena are taken into account, like cache misses, pipeline stalls, and internal/external memory accesses. The model for the algorithm expresses the algorithms influence over the processors activity. The prediction model represents the behavior of the compiler, and how it will allow the algorithm to use the processors resources. The data mapping is considered at that stage. We have developed a tool, SoftExplorer, which performs estimation both at the C-level and the assembly level. Estimations are performed on real-life digital signal processing applications with average errors of% at the C-level and% at the assembly level. We present how SoftExplorer can be used to optimize the consumption of an application. We first show how to find the best data mapping for an algorithm. Then we demonstrate a method to choose the processor and its operating frequency in order to minimize the global energy consumption.

SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level

We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the influence of the data mapping is characterized. Several models of processor are available, from the simple RISC ARM7 to the very complex VLIW DSP TI-C67. Cache misses, pipeline stalls, and internal / external memory accesses are taken into account. We show how to analyze and optimize the power and energy consumption, and how to choose a processor and its operating frequency, for a MPEG-1 decoder. We also explain how to find the best data mapping for a DSP application.

Power Consumption Estimation of a C Program for Data-Intensive Applications

A method for estimating the power consumption of an algorithm is presented. The estimation can be performed both from the C program and from the assembly code. It relies on a power model for the targeted processor. Without compilation, several targets can be compared at the C-level in order to rapidly explore the design space. The estimation can be refined afterwards at the assembly level to allow further code optimizations. The power model of the Texas Instrument TMS320C6201 is presentedas a case study. Estimations are performed on real-life digital signal processing applications with average errors of 4.2 % at the C-level, and 1.8 % at the assembly level.

Refining power consumption estimations in the component based AADL design flow

This paper presents a method that permits to quickly estimate the power consumption at the first steps of a systempsilas design. We present multi-level power models and show how to use them at different levels of the specification refinement in the component based AADL design flow. PET, a power estimation tool, is being developed in the frame of the European SPICES project. It first prototype gives, in the case of a processor binding, power consumption estimations, for software components in the AADL component assembly model, with a maximal error ranging roughly from 5% to 30% depending on the refinement level. We illustrate our approach with the power model of the PowerPC 405, and its use at different levels in the AADL flow.

Energy and Power Consumption Estimation for Embedded Applications and Operating Systems

This paper presents a methodology that permits to estimate the power and energy consumption of embedded applications. Estimation is performed from high-level specifications of the complete system. Power models are built from physical measurements on the hardware platform. Operating system’s services are modeled: scheduler/timer interrupt, inter-process communications, devices accesses models are presented. The operating system’s energy overhead is expressed as the sum of multiple contributions related to services activated during a run. Our methodology is applied to the modeling of a Xillinx Virtex-II Pro XUP platform, and a Linux 2.6 operating system. The comparison of consumption estimations and measurements for different versions of a multi-threaded MJPEG application shows an error ranging from 1% to 11%. Our methodology and power models have been integrated in a CAD tool, named CAT (Consumption Analysis Toolbox), deployed in the Eclipse IDE and also included in the Open Source AADL Tool Environment, bringing energy estimation capabilities in the AADL design flow.

High-Level Interconnect Delay and Power Estimation

It is now well admitted that interconnects introduce delays and consume power and chip resources. To deal with these problems, some studies have been done on performance optimization. However, as the results presented in this paper show, such techniques are not based on good criteria for interconnect performance optimizations. We have, therefore, developed a high-level estimation tool based on transistor-level characteristics, which provides fast and accurate figures for both time and power consumption. These results allowed us to create a new interconnect consumption model and also to determine new key issues that have to be taken into account for future performance optimizations.

Model Driven High-Level Power Estimation of Embedded Operating Systems Communication Services

This paper presents a System level Model Driven Architecture (MDA) approach for power estimation of real time operating system (RTOS) communication and synchronization services at early design phases.The approach integrates the Architecture Analysis and Design Language (AADL) in the design flow. We describe how to extend the language for modeling RTOS communication and synchronization services, and we explain how power consumption analysis can be performed on software components in the AADL platform independent model (PIM), once deployed into components in the AADL target hardware platform model. Operating system services are considered as components in the MDA approach in order to take them into account in the estimation methodology. This paper focuses on consumption analysis of RTOS communication and synchronization services.

Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor

A complete methodology to estimate power consumption at the Clevel for on-the-shelf processors is introduced. It relies on the Functional-Level Power Analysis, which results in a power model of the processor that describes the consumption variations relatively to algorithmic and configuration parameters. Some parameters can be predicted directly from the C-algorithm with simple assumptions on the compilation. Maximum and minimum bounds for power consumption are obtained, together with a very accurate estimation; for the TI C6x, a maximum error of 6% against measurements is obtained for classical digital signal processing algorithms. Estimation results are summarized on a consumption map; the designer can compare the algorithm consumption, and its variations, with the application constraints.