John A. Zoutendyk

Characterization of multiple-bit errors from single-ion tracks in integrated circuits

The spread of charge induced by an ion track in an integrated circuit and its subsequent collection at sensitive nodal junctions can cause multiple-bit errors. The authors have experimentally and analytically investigated this phenomenon using a 256-kb dynamic random-access memory (DRAM). The effects of different charge-transport mechanisms are illustrated, and two classes of ion-track multiple-bit error cluster are identified. It is demonstrated that ion tracks that hit a junction can affect the lateral spread of charge, depending on the nature of the pull-up load on the junction being hit. Ion tracks that do not hit a junction allow the nearly uninhibited lateral spread of charge. >

Lateral charge transport from heavy-ion tracks in integrated circuit chips

A 256 K DRAM has been used to study the lateral transport of charge (electron-hole pairs) induced by direct ionization from heavy-ion tracks in an IC. The qualitative charge transport has been simulated using a 2-D numerical code in cylindrical coordinates. The experimental bit-map data clearly show the manifestation of lateral charge transport in the creation of adjacent multiple-bit errors from a single heavy-ion track. The heavy-ion data further demonstrate the occurrence of multiple-bit errors from single ion tracks with sufficient stopping power. The qualitative numerical simulation results suggest that electric-field-funnel-aided (drift) collection accounts for single error generated by an ion passing through a charge-collecting junction, while multiple errors from a single ion track are due to lateral diffusion of ion-generated charge. A quantitative analysis of this effect would require that the simulation be extended to adjacent devices and would therefore require a 3-D numerical code in Cartesian coordinates. >

Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a new SEU mode in an on n-channel device is presented.

Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and 0 ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Theoretical analysis of heat flow in horizontal ribbon growth from a melt

A theoretical heat flow analysis for horizontal ribbon growth is presented. Equations are derived relating pull speed, ribbon thickness, thermal gradient in the melt, and melt temperature for limiting cases of heat removal by radiation only and isothermal heat removal from the solid surface over the melt. Geometrical cross sections of the growth zone are shown to be triangular and nearly parabolic for the two respective cases. Theoretical pull speed for silicon ribbon 0.01 cm thick, where the loss of latent heat of fusion is by radiation to ambient temperature (300 K) only, is shown to be 1 cm/sec for horizontal growth extending 2 cm over the melt and with no heat conduction either to or from the melt. Further enhancement of ribbon growth rate by placing cooling blocks adjacent to the top surface is shown to be theoretically possible.

Analysis of forced convection heat flow effects in horizontal ribbon growth from the melt

Abstract A heat transfort analysis which considers forced convective fluid flow induced by the motion of a continuous solid ribbon over a melt has been done for horizontal ribbon growth. A model has been developed which treats both “active” and “passive” cooling at the ribbon surface. The results show that heat flow from the melt requires active cooling in the region of the leading growth edge or growth tip. Steady-state liquid-solid interface shape is analyzed and numerical results are given for steady-state pulling of silicon ribbon.

Response of a DRAM to single-ion tracks of different heavy-ion species and stopping powers

Multiple-bit errors caused by single-ion tracks in a 256-kb DRAM fabricated by a bulk process were observed for different ion species and stopping power values. The results demonstrate the utility of this device for the evaluation of ion-beam uniformity and ion-beam-induced charge collection in IC devices. The data indicate that single-ion-induced charge transport results in multiple-bit error clusters due to lateral diffusion of excess minority carriers (electrons). Charge collection occurred from a depth of up to 35 mu m from te surface of the device. An apparent charge loss was observed for very heavy ions with a high stopping power (Au at 350 MeV). >

Modeling of Single-Event Upset in Bipolar Integrated Circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Single Event Upset Immune Integrated Circuits for Project Galileo

Tests and analysis showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and have upset immunity in excess of the mission requirement (upset LET threshold > 37 MeV/mg/ cm2).

Single-Event Upset (SEU) in a Dram with On-Chip Error Correction

The results are given of the first SEU measurements ever reported on IC devices with on-chip error correction. This method of SEU abatement could revolutionize the design of SEU-immune electronic systems.