John Barry Griswell

Stretching the limits of clock-gating efficiency in server-class processors

Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realistic benefits and limits of clock-gating in current generation high-performance processors (e.g. of the POWER4/spl trade/ or POWER5/spl trade/ class). We then look beyond classical clock-gating: we examine additional opportunities to avoid unnecessary clocking in real workload executions. In particular, we examine the power reduction benefits of a couple of newly invented schemes called transparent pipeline clock-gating and elastic pipeline clock-gating. Based on our experiences with current designs, we try to bound the practical limits of clock gating efficiency in future microprocessors.

Power-performance comparative evaluation of alternate microarchitectures

This article consists of a collection of slides from the authors conference presentation. Some of the specific areas/topics discussed include: Power Dissipation and Efficiency Basics; POWER4 vs. POWERS; POWERS vs. POWER6; Roadrunner and Blue Gene System Efficiency; Conclusion; BACKUP: Looking Ahead: A Few Key Research Issues.