John Christopher Willis

Optimizing VHDL compilation for parallel simulation

Auriga, an experimental simulator that utilizes five compilation techniques to reduce runtime complexity and promote concurrency in the simulation of VHDL models is described. Auriga is designed to translate a model using any VHDL construct into an optimized, parallel simulation. Aurigas distributed simulation uses a message-passing network to simulate a single VHDL model. The authors present results obtained with seven benchmark models to illustrate the compilers aggressive optimization techniques: temporal analysis, waveform propagation, input desensitization, concurrent evaluation, and statement compaction.<<ETX>>

The advanced intermediate representation with extensibility/common environment (AIRE/CE)

Todays electronic system designers are faced with steadily increasing pressures to deliver greater functionality at less cost in less time. The Advanced Intermediate Representation with Extensibility/Common Environment, AIRE/CE, addresses these pressures by providing fundamentally new capability to both integrate state-of-the-art tool components into a programs design now and exchange partially compiled hardware/system designs.

High-performance hardware description language simulation: modeling issues and recommended practices

Parallel simulation of hardware description languages (HDL) is no longer solely a subject of largely academic interest; it is now a significant opportunity for mainstream hardware and system designers. System requirements and system fabrication densities often exceed uni-processor simulation capability, while shared-memory multiprocessors, high-speed networks and parallel processors (platforms) are widely accessible. However, recognition and practice of suitable HDL modeling practices are critical to efficiently satisfying performance requirements using parallel tool capabilities. This paper develops a set of recommended modeling practices intended to boost parallel HDL simulation effectiveness. These modeling practices are part of an effort by the IEEE Design Automation Standards Committee (DASC) group on High Performance Modeling for Simulation (HPMSIM) to develop a set of recommended practices for discrete-event and continuous-domain modeling in VHDL, VHDL-AMS and Verilog. Since the optimal modeling style is tightly related to the parallel machine architecture employed and the simulation algorithms used, both this paper and the DASC effort key specific modeling recommendations to processor architecture and simulation algorithm classes. Parallel simulators are a technical and commercial reality, thanks in part to the intrinsically parallel nature of HDLs, especially VHDL and VHDL-AMS. Simulation efficiency achieved when using such simulators is heavily dependent on the modeling style used to write the

Automating the Validation of Hardware Description Language Processing Tools

Testing the adherence of a hardware description language (HDL) tool to an associated HDL specification is of critical importance to design teams. This paper will develop practical test suite requirements, outline FTL System’s VIVATM technology for automatically generating and applying test suites, and describe the experimental results using VIVA (VHDL Interactive Validation Alchemy) to test FTL Systems’ Auriga ® family of HDL compilers.