Steven Lee Gregor

A building block BIST methodology for SOC designs: a case study

System-on-Chip (SOC) designs use numerous and diverse embedded cores and memories. Very high system reliability requirements mandate greater than 99.9% ATPG chip manufacturing test coverage. Logic BIST and memory BIST are increasingly used for high system test coverage with additional constraints that some cores or pockets of user designed logic have to be functionally active during BIST. This paper describes the challenges of a design methodology to handle such SOC designs and the automated solutions that address these problems.