John Critchlow

A 1.6Gb/s/pair electromagnetically coupled multidrop bus using modulated signaling

AC coupling and pulse modulation are presented for high speed multidrop busses. A prototype eight module memory bus operates at a 400MHz symbol rate with 4 bits of modulated data per symbol, for 1.6Gb/s/pair. Test chips in 0.25/spl mu/m 3M CMOS dissipate 40mW peak and occupy 340/spl times/200/spl mu/m per pair.

An alignment insensitive separable electromagnetic coupler for high-speed digital multidrop bus applications

A separable electromagnetic coupler was designed, simulated, fabricated, and tested as part of a prototype eight-module multidrop memory bus. The coupler consists of broadside coupled traces, one on a rigid motherboard and the other on a flex circuit soldered to a daughter card. The zig-zag geometry of the traces reduces variation in the coupling coefficient due to horizontal and vertical misalignment of the coupler halves. Simulation and testing indicates that a target capacitive coupling coefficient of 0.34, which has been selected to balance signal-transmission-level requirements against motherboard impedance discontinuity effects, can be achieved with little variation over +/-12-mil alignment tolerance. In addition, custom interface circuitry was designed in conjunction with the coupler to enable 1.6-Gb/s data rate per differential pair. The prototype system was tested for an extended period executing read and write memory transactions for an estimated bit error rate less than 2.0e-17.