John D'Amico

The Present Status and Recent Advancements in Corona-Kelvin Non-Contact Electrical Metrology of Dielectrics for IC-Manufacturing

Non-contact electrical metrology offers a fast and cost saving monitoring of dielectrics in IC manufacturing process. This corona-Kelvin measuring technique has entered the maturity stage with about 400 tools installed in silicon IC-fabs. We discuss recent advancements that broaden the spectrum of monitoring parameters and enhance the precision of these measurements. We also discuss the current ongoing extension of corona-Kelvin metrology to the micro scale measurement on sites as small as 30µm x 30µm. This opens new possibilities for non-contact electrical testing of product wafers, rather than expensive process monitor wafers. Micro-measurement is illustrated using flash memory ONO structures and corona induced programming and erasing.

Multifunction metrology platform for photovoltaics

Advanced characterization for PV is a complex process that must address bulk defects, interfaces, passivation, and degradation phenomena. It requires not only appropriate measurement techniques, but also a coupling of measurements with treatments altering defect/interface activity. Preferably, the metrology should be noncontact and cost effective. The purpose of this work was to provide such multifunction wafer scale characterization capability for silicon PV. In this paper we describe a multifunction metrology platform. Example applications are given that illustrate the importance of sequenced measurements for 1 — monitoring of the light induced degradation in PV wafers and solar cells; 2 — correlation between interface trap density and surface recombination and the role of surface barrier, and 3 — monitoring of the field-effect potential emitter passivation.

Importance of defect photoionization in silicon-rich SiN x dielectrics for high PID resistance

We demonstrate the presence of significant defect-induced photoconductance in silicon-rich SiNx films that creates high resistance to potential induced degradation, PID, of silicon photovoltaic modules. This photoconductance phenomenon is extrinsic in nature. It originates from the photoionization of deep defect levels in SiNx, rather than from the much higher energy band-to-band carrier generation involved in intrinsic photoconductance. The defect photoconductance is not present in the IR spectral range. Its onset appears in the visible red light range indicating deep levels with an energy separation from the SiNx bands edges of about 1.8eV. The photoconductance is significantly less in stoichiometric Si3N4 films while appearing in films deposited under silicon-rich conditions and especially in films with a refractive index above n=2.05. The deep level photoionization rate (and the magnitude of the photoconductance) increases in films with larger n and indicates a higher concentration of defects related to excess silicon in the SiNx. The present study was performed using semiconductor industry proven corona charging CV metrology that provides noncontact quantitative characterization of dielectric and interface charges, surface and interface potentials, and dielectric leakage currents. Measurements were carried out on sister wafers to those in a modular PID susceptibility study.

Study of Stress-Induced Leakage Current in Thin Oxides Stressed by Corona Charging in Air: Relationship to GOI Defects

Corona charging in air combined with non-contact oxide charge measurement with a contact potential difference probe provides an unique possibility for fast monitoring of electron tunneling characteristics without preparation of MOS capacitors. It has also been found tha corona charging of thin oxides in the tunneling range is very effective in generating stressinduced leakage current. In this work we demonstrate the sensitivity of the corona stressinduced leakage current magnitude to gate oxide integrity defect density. The experimenta results cover three of the most common gate oxide integrity defects, namely: 1 – the defect induced by heavy metals (Fe.Cu) at a practically important low concentration range of 1×10 10 to 1×10 11 atoms/cm 3 : 2 – the defects originating from interface roughness and 3–the defects related to crystal originated particles. At low corona stress fluence, these defects play no role in the tunneling characteristics which follow ideal Fowler-Nordheim characteristics for oxides 50A or thicker and a contribution from a direct tunneling current for thinner oxides. At high corona stress fluences, gate oxide integrity defects control the magnitude of stress-induced leakage current measured at constan oxide field. It is suggested that the gate oxide integrity role is associated with the enhanced rate of the trap generation during stress. It is noted that the present findings employ a novel methodology for gate oxide integrity monitoring based on corona charging and contact potential difference measurement.

Effect of Fe and Cu contamination on the reliability of ultrathin gate oxides

The detrimental effect of heavy metal contamination on gate oxide reliability has been well documented for oxides thicker than 7 nm. This study offers evidence of the detrimental effect that metallic (Fe, Cu) contamination has on ultra-thin gate oxide reliability. Oxides grown at 850 degrees Celsius of 3.5 and 7 nm thickness were intentionally contaminated with Fe (pre-oxidation) or Cu (pre- and post-oxidation.) Bulk silicon FE concentrations of 5 X 1010 to 1 X 1013 atoms/cm3 were achieved through the spin doping of an aqueous FeCl3 solution on the wafer surface prior to oxidation. Pre-oxidation Cu contamination was attained through full wafer immersion in a 10:1 HF:H2O solution contaminated with CuSO4 of varying Cu concentrations (1 ppb to 100 ppb), while post-oxidation contamination results from a 30 minute 450 degree Celsius forming gas anneal which drives in Cu previously deposited on the backside of the wafer. A new corona-based technique was used to measure the stress-induced leakage current (SILC) characteristics of the contaminated and control oxides after various stress fluences, from 10-5 to 10-1 C/cm2, in either the Fowler-Nordheim or the direct tunneling regime for the 7 and 3.5 nm oxides respectively. This non-contact technique employing the COCOS (Corona Oxide Characterization of Semiconductor) methodology measures current flowing through the oxide as a function of the oxide electric field induced by corona. In addition, electrical measurements on MOS capacitors were performed and the results compared to COCOS SILC results. For the 7 nm oxides, COCOS measurements clearly showed enhanced SILC due to metallic contamination confirming previous findings. For the 3.5 nm oxides, two distinct features were established: (1) pre-stress I-V characteristics were consistent with a direct tunneling mechanism exhibiting a distinct shift to higher currents at lower electric fields and (2) the SILC was smaller in magnitude than that exhibited by the 7 nm oxides. Existing SILC models (i.e. trap-assisted tunneling) were used to interpret the I-V data. In addition, this stress resulted in oxide wearout, which produced noticeable flat-band shifts and an order of magnitude increase in interface state density, also measured using the COCOS technique. The effect of metallic contamination on these wearout issues was also investigated.

Inline PL Inspection and Advanced Offline Evaluation of Passivation Defects, Charge and Interfaces

Recently introduced techniques for whole wafer mapping and imaging create new possibilities for root cause analysis of emitter passivation defects. Inline compatible PL imaging identifies such defects as localized regions with increased emitter saturation current and reduced implied open circuit voltage. Advanced offline evaluation of defective areas can be then performed with multiparameter noncontact measurements capable to establish the role of surface recombination, the interface trap density, or the dielectric charge that controls the field-effect passivation. The relevant novel metrologies are discussed and are illustrated using examples of advanced silicon passivation by dielectric films and by a-Si heterojunction structures.

Non-Visual Defect Monitoring with Surface Voltage Mapping: Application for Semiconductor IC and PV Technology

Non Visual Defects (NVD) is a category of defects that cause electrical failures but are not detected with visual wafer inspection tools. Our approach for NVD detection is based on the Kelvin probe surface voltage mapping technique. The detection of defects is enhanced using field-effect created in a non-contact manner by corona charge deposition on the surface of semiconductor. Precise defect location is accomplished with surface voltage gradient magnitude mapping that enhances delineation of defects. Detected defects are characterized locally using the corona-voltage technique or isothermal voltage transient decay analysis. Presented examples include: dielectric charge and interfacial defect mapping on 300mm Si wafers; deep level emission mapping on epitaxial SiC and mobile ion mapping in Si solar cells.

Experimental study on the role of parameters affecting surface recombination and emitter passivation

A multifunction metrology platform for silicon photovoltaics introduced about 3 years ago has helped generate experimental data demonstrating the importance of different electrical parameters that affect the surface recombination and corresponding passivation of PV emitters for advanced solar cells. In this paper we outline unique capabilities provided by mapping of multiple electrical properties. Interface trap density data are presented for Si passivated with Al2O3 and for a-Si/SiNx heterointerfaces. Using examples of corresponding multi-parameter data it is also shown that surface recombination can be increased or decreased depending on the value of the silicon space charge barrier, interface trapped charge and dielectric charge. For emitter structures the latter effect determines the effectiveness of field effect passivation and the value of the emitter saturation current, J0. The results reviewed in this paper illustrate potential paths to cell efficiency improvements by elimination of defective wafer areas with high Dit or with dielectric charge values away from low J0 field effect saturation. In this respect, the wafer mapping approach offers significant practical advantages as compared to a study involving multi-sample preparation and single point measurements.

Recent Advancement in Charge and Photo-Assisted Non-Contact Electrical Characterization of SiC, GaN, and AlGaN/GaN HEMT

The charge-based corona-Kelvin noncontact metrology, originally developed for Si IC fabrication, has recently been extended to wide energy gap semiconductors. We discuss principles of this extension and key applications, namely: high precision dopant measurement on SiC and GaN; two-dimensional electron gas characterization in AlGaN/GaN HEMT structures; interface and dielectric characterization on epi-layers with SiO2, SiN and Al2O3; comprehensive interfacial instability characterization of oxidized SiC; and whole wafer mapping of defects with a charge-assisted surface voltage technique. This powerful set of measurements is performed without fabrication of any test structures or electrical contact. Corresponding commercial tools are currently being introduced. Based on the historical example of silicon IC, we believe that this approach shall offer enhanced testing for research and for manufacturing process control with reduced cost and fast data feedback benefiting the wide-bandgap device technology.

State-of-the-art multiparameter characterization of the chemical and field effect passivation of very high lifetime n-Si with n+ front surface field (FSF)

An effective characterization approach for n⁺ front surface field (FSF) passivation has been developed using a sequence of state-of-the-art “corona charge-Kelvin” electrical methods integrated with lifetime based monitoring using QSS-μPCD with a decay control method. The approach was applied to symmetrical test structures on high lifetime n-Si with n⁺ FSF typically used in high efficiency IBC cells. Test structures with similar SiN_x-based top dielectric included structures with and without n⁺ FSF. Structures without the FSF enabled complete dielectric and interfacial charge characterization. The D_it spectra revealed very low interface trap density with midgap values about 3e10 q/cm²eV. This D_it implies excellent chemical passivation. In addition, classical field-effect response of the effective carrier lifetime vs. corona charge showed a lifetime minimum near zero charge (corresponding to a maximum surface recombination velocity) and an increase of lifetime in inversion and accumulation for the structure without n⁺ FSF. For n⁺ FSF structures lifetimes higher than that for undoped structures were measured. The 12ms maximum effective lifetime measured for the n⁺ FSF structure with QSS-μPCD indicates maximum effective surface recombination around 0.5 cm/s, while for the structure without n⁺ FSF the maximum effective lifetime was about 1.7ms. For the n⁺ FSF structure, the field-effect characteristics of τ_eff demonstrated very high lifetime for zero charge and for positive corona charge. The overall results indicate that excellent n⁺ FSF passivation is a consequence of three elements: 1. good chemical passivation 2. good surface field passivation and 3. close to optimal dielectric charge controlled field-effect passivation. The surface saturation current measurements revealed J₀ = 5.1fA/cm² that would correspond to V_OC ~ 751mV, consistent with cell results reported for advanced IBC cells. Whole wafer mapping showed good n⁺ FSF passivation uniformity with J₀ from 5 to 7fA/cm² in 95% of the wafer. The present metrology approach required important technology refinements that are now being introduced in PV2000A tools developed by Semilab SDI.