John J. Bergkvist

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

This paper describes the design of a product-level low-power source-synchronous link receiver macro for data rates of 3.2-6.4 Gb/s. The receiver macro consists of 22 data channels plus one forwarded-clock channel, and supports both differential and ground termination. A pulsed CDR with programmable bandwidth is implemented to save power in the CDR. Time dithering is applied to the CDR to avoid notches in the jitter tolerance curve. The receiver clock path incorporates both a clean-up PLL and a polyphase filter for RX clock generation, from which one can be chosen to generate the receive clock. It is shown how jitter in a source-synchronous link is related to skew between clock and data, as well as cross-talk from the data to the clock wires. The jitter performance of the RX using either the polyphase filter or the PLL for clock generation is compared for different loop bandwidths. The RX core was implemented in a 65 nm Bulk CMOS technology. Total power consumption for the 22+1 lane RX PHY core running at 6.4 Gbps with the polyphase filter and in pulsed CDR mode is 635 mW or 4.5 mW/Gbps.

A 5 ns store barrier cache with dynamic prediction of load/store conflicts in superscalar processors

Many superscalar processors support out-of-order instruction execution and executes multiple instructions per cycle. One of the hazards of executing instructions out of order occurs when a prior instruction store is at the same memory location as a later instruction load, but the execution of the load occurs before the store is complete. Dynamic prediction about a store instruction involved in a load/store hazard can be used to delay a load instruction execution that is later in program order. The load/store conflict-prediction mechanism consists of a two-way set associative, 32-entry, two-ported SRAM cache used to contain information on store instructions involved in load/store conflicts.

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.