John L. Prince

Rigorous electromagnetic modeling of chip-to-package (first-level) interconnections

A methodology is presented for the rigorous electromagnetic analysis of pulse transmission through first-level interconnects. The methodology combines a full-wave, vectorial, time-dependent Maxwells equations solver with SPICE circuit models for the nonlinear drivers, to facilitate the accurate modeling of the electromagnetic phenomena occurring at the chip-to-package interface. Comparisons of the results obtained using this method with others calculated using SPICE simulations are used to validate the method and demonstrate its application in the electromagnetic modeling of high-speed packaging structures. >

Effect of CMOS driver loading conditions on simultaneous switching noise

A model for simultaneous switching noise (SSN) for CMOS including the effect of negative feedback and loading conditions is presented. A level 1, SPICE-type device model is used with V/sub TN/=|V/sub TP/| for the simulations. An analysis of the loading conditions is conducted since no prior knowledge of this is assumed in the design of the package. The sensitivity of SSN to the load capacitance is investigated. Equations defining a critical capacitance governing SSN are included. Output buffers normally drive receivers through bond wires, signal traces, pins, and the board traces. For the short trace, the output is modeled as a lumped inductance and for the long trace, as a transmission line. Such a condition at the output will alter the current that defines the noise. Equations are presented for the critical inductance and the transmission line characteristic impedance. Above these critical values, these parameters will tend to decrease the noise generated. Finally, a practical package structure is modeled which takes into account the effects of the total loading conditions. >

Discussion and Future Work

Even though Bipolar Junction Transistor (BJT) output driver current drive capabilities are better than its counterpart CMOS output drivers, they dissipate more power. For high level integration Multi-Chip Modules (MCMs), power-delay product is an important performance metric in system performance evaluation. With advancement in CMOS process technology in the last decade, high level of integration can be achieved by using CMOS technology compared to BJT technology. However, one of the trade-off is between speed and integration. With the advancements in scaled(Leff <0.75µm) CMOS technology, preliminary trade-off studies have shown that possible technology map for high performance computers will move from BJT to BiCMOS and eventually to CMOS technology [11.1].

Improved global rational approximation macromodeling algorithm for networks characterized by frequency-sampled data

Recently, the demand for high-performance wireless designs has been increasing while simultaneously the speed of high-end digital designs have crossed over the gigahertz range. New simulation tools which accurately characterize high-frequency interconnects are needed. This paper presents improvements to a new macromodeling algorithm. The algorithm employs curve-fitting techniques to achieve a pole-residue approximation of the frequency-sampled network. The frequency sampled S-parameters or Y-parameters can be obtained from measurement or full-wave simulation to characterize the frequency-dependent interconnects behavior. The improvements extend the approach to lossless structures, increase its accuracy with pole-clustering, and ensure its validity with a passivity test. This paper addresses some of the special considerations that must be made to the method so it can efficiently and accurately be applied to lossless circuits and structures. The resulting algorithm is now capable of accurately extracting a wide-band frequency domain macromodel from frequency-sampled data for either LC circuit (lossless) or RLC circuits (lossy). The frequency-domain macromodel can be linked to a SPICE circuit simulator for mixed signal circuit analysis using RF, analog, and digital circuits. The circuit can be simulated in the time domain using recursive convolution.

Frequency-dependent inductance and resistance calculation for three-dimensional structures in high-speed interconnect systems

Frequency-dependent inductances and resistances of three-dimensional structures commonly encountered in modern electronic interconnections are calculated by a combined finite-element/integral-equation method. the mathematical formulation and the numerical method of solution are discussed. Numerical results for microstrip bends and vias are presented. These results compare well with experiment. The effect of the frequency dependence of the inductance on pulse propagation is discussed. >

A new discrete transmission line model for passive model order reduction and macromodeling of high-speed interconnections

A new, computationally efficient, discrete model is presented for passive model order reduction of high-speed interconnections. The proposed discrete model is based on the use of the theory of compact finite differences for the development of the discrete approximation to the transmission line equations that govern wave propagation on the interconnections. Thus result in a discrete model that utilizes only a few unknowns per wavelength and yet provides highly accurate waveform resolution. In addition to improved computational efficiency, the generated discrete model is passive, and compatible with the passive reduced-order interconnect modeling algorithm (PRIMA). Thus, it is suitable for the development of passive reduced-order models of interconnection networks of high complexity. Numerical experiments from the simulation and model order reduction of coupled interconnections are used to illustrate the validity and efficiency of the proposed model.

S-parameter analysis of multiconductor, integrated circuit interconnect systems

The authors explore the use of S-parameter-based network techniques for the analysis of coupled, multiconductor, high-speed analog and digital integrated circuit interconnects. S-parameter-based computer-aided design (CAD) techniques, widely used in microwave network analysis, provide a powerful framework for the analysis of analog and digital integrated circuit interconnect systems. The specific additions to the existing S-parameter network analysis framework developed provide for multiport interconnect capabilities and for the use of multiconductor S-parameters derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G; (2) lossy frequency-dependent (dispersive) R,L,C,G; and (3) the propagation constants, characteristic impedance, and conductor eigencurrents, derived from full-wave electromagnetic analysis. Results are compared with computed simulations and experimental measurements. >

Dielectric constant and loss tangent measurement using a stripline fixture

An approach to dielectric material characterization with a vector network analyzer is presented. As the characteristic impedance (Z/sub 0/) of a stripline transmission line can be accurately determined by measuring the two-port scattering parameters in the frequency range of interest, the dielectric constant of the insulation material that consists of part of the stripline configuration is then obtained by relationship to the characteristic impedance. The dielectric loss (or loss tangent) can be determined by measuring the return loss and the insertion loss of the stripline. The validity of the technique is demonstrated for well-characterized dielectric materials such as Teflon-based and other composite laminates. The technique is then applied to IC molding compounds as processed.A new approach to dielectric material characterization with a vector network analyzer is presented. As the characteristic impedance (Z0) of a stripline transmission line can be accurately determined by measuring the two-port scattering parameters in the frequency range of interest, the dielectric constant of the insulation material that consists as part of the stripline configuration is then obtained by a relationship to the characteristic impedance. The dielectric loss (or loss tangent) can be determined by measuring the return loss and the insertion loss of the stripline. The validity of the technique is demonstrated for well-characterized dielectric materials such as Teflon-based and other composite laminates. The technique is then applied to integrated circuit (IC) molding compounds as-processed.

Electrical Modeling of Interconnections in Multilayer Packaging Structures

An effort toward modeling the interconnections in selected typical multilayer packaging structures is presented. The modeling is based on a quasi-static approximation to the associated electro-magnetic problems. A program for computing capacitance and inductance matrices and the numerical techniques used to improve the program efficiency are described. The results of numerical testing of the program are provided and discussed. The program was also compared with experimental data published in the open literature and the results are shown. The agreement between the model and the experiments is satisfactory.

Performance of Digital Integrated Circuit Technologies at Very High Temperatures

Results of detailed investigations of the performance and reliability of digital bipolar and complementary metal-oxide-semiconductor (CMOS) integrated circuits over the 25-340°C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results from experimental simulations of dielectrically isolated CMOS are also discussed. In general, it was found that commercial Schottky-clamped transistor-transistor logic (TTL) and dielectrically isolated, low power Schottky-clamped TTL functioned to junction temperatures in excess of 325°C. Standard gold-doped TTL functioned only to 250°C, while commercial isolated integrated injection logic (l2L) functioned to the range of 250-275°C. Commercial junction-isolated CMOS, buffered and unbuffered, functioned to the range of 280-310+°C, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340°C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious lifelimiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated circuits at temperatures in excess of 300°C has been found.