Ramesh Senthinathan

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).

Jitter transfer characteristics of delay-locked loops - theories and design techniques

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.

0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

This paper presents a 622 Mbps to 8 Gbps transceiver in standard 0.13 /spl mu/m CMOS technology. Each receiver and transmitter macrocell has its dedicated clock multiplication unit (CMU) and clock/data recovery unit (CDR), providing simultaneous multi-rate operation for multiple lanes on a chip. The transmitter and receiver front-end use direct 4:1 multiplex and 1:4 demultiplexing, using multiple-phase quarter-rate clocks. An automatic phase offset cancellation scheme is used to eliminate the phase mismatch of the multiple clock phases. Each transceiver occupies an active area of less than 0.4 mm/sup 2/ and consumes 150 mW at maximum speed.

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.

A 600 MHz IA-32 microprocessor with enhanced data streaming for graphics and video

This Intel architecture microprocessor (Pentium III) implements 70 additional instructions to further accelerate the performance of data-streaming applications including 3D graphics and video encode/decode. This processor is enhanced by addition of these instructions along with circuit improvements for higher clock frequency. The 10.17/spl times/12.10 mm/sup 2/ die contains 9.5 M transistors and is in a CMOS 5-layer metal 0.25 /spl mu/ process in an OLGA package with C4 interconnect technology. It has an operating range of 1.4 V to 2.2 V and is currently running up to 60O MHz.

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection MUX. For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2 V 0.13 /spl mu/m CMOS CDR consumes 33 mW at 8 Gb/s. Die area, including voltage regulator, is 0.08 mm/sup 2/. Recovered clock jitter is 6.9 ps rms/49.3 ps peak-to-peak at a 200 ppm bitrate offset.

Characteristics of Coupled Buried Microstrip Lines by Modeling and Simulation

Electrical characteristics of coupled buried microstrip lines were obtained using a recently developed two-dimensional TEM transmission line parameter modeling tool. The capacitance [C] and inductance matrix [L] parameters were used in a lossless TEM mode transmission line transient response calculator to determine the maximum coupled noise. It is found that there is a critical depth of bury h c below which the lines appear to be within an infinite dielectric and above which there is coupling to the polarization charge on the dielectric interface. This often results in very complicated Coupled noise behavior as the coupling of the lines is capacitive at One depth of bury and inductive at another depth of bury. Parameter simulation and maximum noise results are given for a wide variety of structures important in integrated circuit electronic packaging structures.

20Gb/s 0.13/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20Gb/s transmitter is implemented in 0.13/spl mu/m CMOS technology. Eight 2.5Gb/s data streams are 4:1 multiplexed, sampled, and retimed into two 10Gb/s data streams. A final 20Gb/s 2:1 output multiplexer, clocked by complementary phases of an LC-VCO (voltage controlled oscillator) in a phase-locked loop, creates 20Gb/s data. The VCO is integrated with the output multiplexer, resonating the load and eliminating the need for clock buffers. Power, active die area, and jitter (RMS/pk-pk) are 165mW, 650/spl mu/m /spl times/ 350/spl mu/m, and 2.37ps/15ps, respectively.