John M. C. Covington

Performance of digital discrete-time implementations of non-Foster circuit elements

There is renewed interest in the use of non-Foster circuit elements in a variety of important applications such as wideband impedance matching and artificial magnetic conductors. Although non-Foster devices such as negative capacitors and negative inductors can be realized using current conveyors and Linvill circuits, a digital design approach may offer an important alternative in some applications. Therefore, digital discrete-time implementations of non-Foster circuit elements are investigated, and simulation results are presented for the implementation of a discrete-time negative inductor and a discrete-time negative capacitor.

Stability conditions for a digital discrete-time non-Foster circuit element

Digital discrete-time implementations of non-Foster circuit elements offer an alternative to conventional analog circuit approaches. In particular, the design of a discrete-time negative capacitor is investigated, since such non-Foster circuit elements offer significant potential in wideband antenna, metamaterial, and artificial magnetic conductor applications. As with analog non-Foster circuits, stability is an important design consideration for digital non-Foster elements. Therefore, stability conditions and simulation results are presented for a discrete-time negative capacitor, and the onset of instability is shown near the predicted stability boundary.

Measurement of a CMOS negative inductor for wideband non-foster metamaterials

There is increasing interest in impedance-matching methods that use non-Foster circuits to provide wideband operation in a variety of microwave devices such as antennas and metamaterials. In addition, many of these prior non-Foster circuits employ bipolar negative impedance converter designs, and it is advantageous to move such designs into CMOS. Therefore, the present work provides new measured results building upon an earlier proposed design of a negative inductor in a 0.5 micron CMOS process. The proposed circuit eliminates a resistor from a common negative impedance converter topology, and the prototype performs well at high frequency. Measured results show a low-frequency inductance of -95 nH falling to -85 nH at 750 MHz and -63 nH at 1 GHz. Finally, simulation results are presented for the performance of the circuit in a metamaterial application.

A DC-coupled negative inductance circuit with integrated bias

Negative inductance circuits offer the potential for increased bandwidth in a variety of applications such as artificial magnetic conductors and metamaterials with negative permeability. To address such applications, a CMOS dc-coupled negative inductance circuit with integrated presented. The dc-coupled input is tailored voltages and accommodate applications having an inductive load in series with a low resistance. An integrated bias circuit is used to allow operation with a single power supply and to eliminate the need for a separate input bias. In addition, the parasitic capacitance of the CMOS transistors in the basic negative impedance inverter is used to set the negative inductance of the overall circuit. Results are presented that show a negative inductance of -11 0 nH in a 0.5 micron CMOS process.

Comparison of CMOS current conveyor circuits for non-Foster applications

Current conveyors are an important component implementing non-Foster circuits such as negative capacitors negative resistors. However, different topologies exist for implementing negative capacitance using a current conveyor, and the performance of such topologies can vary greatly. Therefore, this paper considers two competing realizations of negative capacitance using a current conveyor, where both circuits are designed for -5 pF in a 0.5 micron CMOS process. Simulation results are presented that show significant bandwidth differences for the two -5 pF designs, where one approach has more than twice the bandwidth of the second approach.

A cross-coupled cmos negative capacitor for wideband metamaterial applications

Non-Foster circuits can be used to provide broadband impedance matching for antennas and metamaterials. These circuits allow effective matching over a much wider bandwidth than is expected from traditional passive components. Therefore, this paper considers the design and test of a negative capacitor in a 0.5 micron CMOS process. The proposed circuit uses a cross-coupled design to allow for floating operation, and the designs simulated performance works well at high frequency. Measured results show a low-frequency capacitance of -1.7 pF and within 10% to 200 MHz, and falling to -4 pF at 230 MHz. Although the selected CMOS process is adequate to demonstrate the basic design approach, more advanced process nodes would be expected to extend performance to even higher frequencies. Results are also presented showing performance of the circuit in a metamaterial.

Measurement and simulation of a CMOS current conveyor negative capacitor for metamaterials

Current conveyors can be used as building blocks for implementing non-Foster circuits such as negative capacitors and negative inductors that are useful in extending bandwidth in metamaterials. In the present paper, measured results are presented for a prototype integrated circuit current conveyor negative capacitor. This circuit has been fabricated in a 0.5 micron CMOS process following previous results. Although CMOS is a desirable technology for circuit implementation, it is accompanied by design challenges of associated parasitic resistance. To investigate these issues, a prototype second generation current conveyor (CCII) is designed and tested in a negative capacitance circuit. In addition, full-wave electromagnetic simulation results are also presented showing the effects of observed resistance on overall metamaterial performance.

Capacitance and bandwidth tradeoffs in a cross-coupled CMOS negative capacitor

Recent advances in technology have driven renewed interest in the design of CMOS negative capacitance circuits for diverse applications such as wideband metamaterials and radio frequency integrated circuits. In practice, the particular CMOS fabrication process generally limits the practical range of capacitance values and bandwidths that can be achieved. In addition, the reactive component of the desired impedance is often accompanied by a parasitic resistive component. To address these issues, a CMOS cross-coupled negative capacitance circuit is designed and simulated in a 0.5 micron CMOS process. Results are presented for -5 pF, -10 pF, and -20 pF designs with ten-percent bandwidths of approximately 140 MHz, 100 MHz, and 80 MHz respectively.

Permeability and permittivity extraction issues for non-Foster and active metamaterials

Although a variety of methods have been proposed for the extraction of effective permittivity and permeability of metamaterials, certain underlying passivity constraints and assumptions would not be suitable for non-Foster metamaterials that incorporate active devices and power sources. Moreover, recent arguments suggest that a common passivity constraint in extraction methods does not resolve solution branch ambiguities. To address these issues, the fundamental principles of parameter extraction are revisited for the case of active materials where passivity cannot be assumed. The analysis follows along the lines of Nicolson-Ross-Weir approaches, where parameters are extracted from measured two-port S-parameters. It is shown that a convergence constraint for active materials requires that the magnitude of the product of the transmission coefficient and reflection coefficient must be less than unity. This allows metamaterials with gain, and simulation results are provided for a slab of active material that exhibits gain and satisfies the constraint.

Compensation of Frequency Dependent Parasitic Resistance in a CMOS Linvill Negative Inductor

This paper presents an effective approach for reducing parasitic resistance of a CMOS negative inductor with a single compensating resistor. A compensating resistor is used to mitigate the effect of parasitic resistance with quadratic frequency dependence. The undesired parasitic effect is induced by the inevitable finite drain-source resistance of the input CMOS transistor of the most common Linvill negative inductor configuration. In particular, a two-transistor Linvill negative impedance inverter is considered. Theoretical analysis and circuit simulations show that the parasitic CMOS drain-source resistance leads to this undesired quadratic frequency dependency, and the proposed simple compensation circuit is effective. Measured results are given for a prototype CMOS circuit demonstrating the proposed compensation method.