John M. Ludden

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server™ G4. For POWER4, verification began at the abstract, high-level design phase and continued throughout the designer and unit levels, the multi-unit level, and finally the multiple-chip system level. The abstract (high-level design) phase permitted early validation of the POWER4 processor design prior to its commitment to HDL. The designer and unit-level stages focused on ensuring the correctness of the microarchitectural components. Multiunitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems. Finally, systemlevel verification tested multiprocessor coherence and system-level function, including processor-to-I/O communication and validation of multiple hardware configurations. In parallel with design and functional validation, verification of reliability functions, performance, and degraded configurations was also performed at most of the levels in the hierarchy.

Industrial experience with test generation languages for processor verification

We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has ken reduced.

Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

This paper describes the methods and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5TM microprocessor and the eServerTM p5 systems based on it. The approaches used were based on migrating the best practices that had been used to verify the POWER4TM chip. The POWER5 chip design posed new challenges to the simulation team with the addition of simultaneous multithreading (SMT) and dynamic power management (DPM). In addition, there was further integration of cache and memory subsystem function onto the POWER5 chip. Since the design complexity had increased from the POWER4 design, the use of test plan coverage tools and techniques was expanded to ensure the maximum effectiveness of each simulation cycle run. A new toolset was also employed to improve the utilization of the large pool of computers used to run batch simulation jobs and to provide more efficient fail reproduction and bug fix management. For the system-level verification, a new test-case-generation tool was utilized which allowed for more targeted testing through a deeper knowledge of the system topology. In parallel with the mainline functional validation, verification of reliability functions and performance attributes also had increased focus for the POWER5 design.

Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems

This paper describes the methods and techniques used to verify the POWER7® microprocessor and systems. A simple linear extension of the methodology used for POWER4®, POWER5®, and POWER6® was not possible given the aggressive design point and schedule of the POWER7 project. In addition to the sheer complexity of verifying an eight-core processor chip with scalability to 32 sockets, central challenges came from the four-way simultaneous multithreading processor core, a modular implementation structure with heavy use of asynchronous interfaces, aggressive memory subsystem design with numerous new reliability, availability, and serviceability (RAS) advances, and new power management and RAS mechanisms across the chip and the system. Key aspects of the successful verification project include a systematic application of IBMs random-constrained unit verification, unprecedented use of formal verification, thread-scaling support in core verification, and a consistent use of functional coverage across all verification disciplines. Functional coverage instrumentation, which is combined with the use of the newest IBM hardware simulation accelerator platform, enabled coverage-driven development of postsilicon exercisers in preparation of bring-up, a foundation for the desired systematic linkage of presilicon and postsilicon verification. RAS and power management verification also required new approaches, extending these disciplines to span all the way from the unit level to the end-to-end scenarios using the hardware accelerators.

Verification of Transactional Memory in POWER8

Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.

Advances in simultaneous multithreading testcase generation methods

Many modern microprocessor architectures utilize simultaneous multithreading (SMT) for increased performance. This trend is exemplified in IBMs Power series of high-end microprocessors which steadily increased the number of threads in a system in its POWER5, POWER6 and POWER7 designs. In this paper we discuss the steady increase in functional verification complexity introduced by each of these designs and the corresponding improvements to SMT verification methods that were necessary in order to cope with the growing verification challenge. We review three different verification technologies which were specifically developed to target SMT aspects of processor designs, and compare their relative advantages and drawbacks. Our focus is on the novel Thread Irritation technique - we demonstrate its effectiveness in finding high quality SMT bugs early in the verification cycle, and show how it was adopted to the post-silicon platform.

Solutions to IBM POWER8 verification challenges

This paper describes methods and techniques used to verify the POWER8™ microprocessor. The base concepts for the functional verification are those that have been already used in POWER7® processor verification. However, the POWER8 design point provided multiple new challenges that required innovative solutions. With approximately three times the number of transistors available, compared to the POWER7 processor chip, functionality was added by putting additional enhanced cores on-chip and by developing new features that intrinsically require more software interaction. The examples given in this paper demonstrate how new tools and the continuous improvement of existing methods addressed these verification challenges.