John Michael Hergenrother

Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

Challenges of gate-dielectric scaling, including the vertical replacement-gate MOSFET

The microelectronics revolution has been enabled by the nearly ideal properties of silicon dioxide and its interface with silicon. Continually thinner gate oxides have been a critical feature of the overall scaling of transistor dimensions for three decades, enabling continued speed improvement even as operating voltages decrease. This era of scaling in thickness of a silicon dioxide insulator will soon come to an end, as gate tunneling current, reduced reliability, and diminishing returns in speed make further reductions impossible or unrewarding. New materials systems may provide some relief, but they have yet to show their ability to replace silicon dioxide. Truly novel approaches, such as the Vertical, Replacement Gate process, which provides more current in the same area by increasing the device perimeter, can address the same issues.

Toward the ultimate storage device: the fabrication of an ultrahigh-density memory device with 193-nm lithography

We describe the fabrication of the worlds smallest fully functional conventional non-volatile memory device using 193 nm lithography for all levels. The cell area of the smallest devices fabricated was 0.0896 micrometers 2. The critical level of the device, to define the channel length, was exposed with an alternating aperture phase shift mask. Floating gate dimensions ranged from 0.080 to 0.14 micrometers . Subsequent lithography, to define the control gate utilized a binary mask with gate dimensions down to 0.16 micrometers . A multi-layer ARC was used to reduce substrate reflections and maintain linewidth control over topography. All levels were exposed with a new single layer chemically amplified resist developed for 193 nm lithography. We will present results for line width control, etch bias, implementation of resolution enhancement techniques as well as issues with process integration.