John Moondanos

A Signal Correlation Guided ATPG solver and its applications for solving difficult industrial cases

The developments of efficient SAT solvers have attracted tremendous research interest in recent years. The merits of these solvers are often compared in terms of their performance based upon a wide spread of benchmarks. In this paper, we extend an earlier-proposed solver design concept called (SCGL) Signal Correlation Guided Learning that is ATPG-based into a family of heuristics. Along with this SCGL family of heuristics, we classify benchmark examples according to their performance using the SCGL heuristics. With this study, we identify the class of problems that are uniquely suitable to be solved by using the SCGL approach. In particular, for solving difficult circuit-based problems at INTEL, our SCGL-based ATPG solver is able to achieve at least an order of magnitude speedup over the state-of-the-art SAT solvers. Our conclusion is that SCGL is an unique solver design concept that can complement heuristics proposed by others for solving circuit-oriented difficult problems.

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination

Formal equivalence verifiers for combinational circuits rely heavily on BDD algorithms. However, building monolithic BDDs is often not feasible for todays complex circuits. Thus, to increase the effectiveness of BDD-based comparisons, divide-and-conquer strategies based on cut-points are applied. Unfortunately, these algorithms may produce false negatives. Significant effort must then be spent for determining whether the failures are indeed real. In particular, if the design is actually incorrect, many cut-point based algorithms perform very poorly. In this paper we present a new algorithm that completely removes the problem of false negatives by introducing normalized functions instead of free variables at cut points. In addition, this approach handles the propagation of input assumptions to cut-points, is significantly more accurate in finding cut-points, and leads to more efficient counter-example generation for incorrect circuits. Although, naively, our algorithm would appear to be more expensive than traditional cut-point techniques, the empirical data on more than 900 complex signals from a recent microprocessor design, shows rather the opposite.

An enhanced cut-points algorithm in formal equivalence verification

BDD-based cut-points verification is widely used informal verification. The authors have recently developed a cut-points verification algorithm that is unique in that it avoids generation of false-negatives and allows simplification of the circuits to be compared based on reconvergence of input variables. Here we describe several refinements and enhancements that lead both to drastic speedup as well increase in capacity. These methods are already implemented in Intels combinational verifier CLEVER and show very promising results on real life examples from the pentium design family.

Generation of shorter sequences for high resolution error diagnosis using sequential SAT

Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design to those hard-to-reach states for activating the errors and for propagating them to observation points, they tend to be very long, which complicates the subsequent diagnosis process. As a key step in reducing the overall diagnosis complexity, we propose a method of generating a shorter error-sequence based on a given long error-sequence. We formulate the problem as a satisfiability problem and employ a SAT solver as the underlying engine for this task. By heuristically selecting an intermediate state Si which is reachable by the given long sequence, the task of finding the transfer sequence from the initial state to the target state can be divided into two easier tasks - finding a transfer sequence from the initial state to Si and one from Si to the target state. Our preliminary experimental results on public benchmark circuits show that the proposed method can achieve significant reduction in the length of the error sequences

TRANS: efficient sequential verification of loop-free circuits

Bischoff et al. (1997) proposed a method for reducing sequential verification of loop-free circuits to combinational verification, by constructing and comparing the so called Timed (ternary) Binary Decision Diagrams (TBDDs). Ranjan et al. (1999) independently re-discovered a similar method. We propose a much more simple and efficient algorithm for constructing TBDDs. Furthermore, we prove the soundness of the algorithm, and describe very briefly a (restricted) new algorithm for generating sequential counter examples. These algorithms are implemented in Intels sequential verification engine, TRANS.

From Error to Error: Logic Debugging in the Many-Core Era

Design and manufacturing of present day Multi-Core microprocessors has to overcome major technology obstacles, particularly in the areas of Power and Validation. More specifically, the state of the Art in the area of validation is such that upwards of 30% of the human resources in a modern microprocessor Design Team are dedicated to it. The term Validation Productivity Gap has been introduced to describe exactly these ever increasing resource requirements. Formal Verification techniques offer one of the technological approaches for addressing many aspects of this validation gap. Therefore it is of paramount importance to develop technologies and methodologies for reducing the time it takes to debug and rectify Logic Errors that are detected by Formal Verification Techniques. Such developments would offer a much needed productivity improvement both in pre- and post-Silicon validation activities.