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Dive into the research topics where Zurab Khasidashvili is active.

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Featured researches published by Zurab Khasidashvili.


foundations of computer science | 1994

The Longest Perpetual Reductions in Orthogonal Expression Reduction Systems

Zurab Khasidashvili

We consider reductions in Orthogonal Expression Reduction Systems (OERS), that is, Orthogonal Term Rewriting Systems with bound variables and substitutions, as in the λ-calculus. We design a strategy that for any given term t constructs a longest reduction starting from t if t is strongly normalizable, and constructs an infinite reduction otherwise. The Conservation Theorem for OERSs follows easily from the properties of the strategy. We develop a method for computing the length of a longest reduction starting from a strongly normalizable term. We study properties of pure substitutions and several kinds of similarity of redexes. We apply these results to construct an algorithm for computing lengths of longest reductions in strongly persistent OERSs that does not require actual transformation of the input term. As a corollary, we have an algorithm for computing lengths of longest developments in OERSs.


formal methods in computer-aided design | 2007

Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification

Daher Kaiss; Marcelo Skaba; Ziyad Hanna; Zurab Khasidashvili

Automatic synchronization (or reset) of sequential synchronous circuits is considered one of the most challenging tasks in the domain of formal sequential equivalence verification of hardware designs. Earlier attempts were based on Binary Decision Diagrams (BDDs) or classical reachability analysis, which by nature suffer from capacity limitations. A previous attempt to attack this problem using non-BDD based techniques was essentially a collection of heuristics aimed at toggling of the latches, and it is not guaranteed that a synchronization sequence will be computed if it exists. In this paper we present a novel approach for computing reset sequences (and reset states) in order to perform sequential hardware equivalence verification between circuit models. This approach is based on the dual-rail modeling of circuits and utilizes efficient SAT-based engines for Bounded Model Checking (BMC). It is implemented in Intels sequential verification tool, Seqver, and has been proven to be highly successful in proving the equivalence of complex industrial designs. The synchronization method described in this paper can be used in many other CAD applications, including formal property verification, automatic test generation, and power estimation.


colloquium on trees in algebra and programming | 1996

Relative Normalization in Deterministic Residual Structures

John R. W. Glauert; Zurab Khasidashvili

This paper generalizes the Huet and Levy theory of normalization by neededness to an abstract setting. We define Stable Deterministic Residual Structures (SDRS) and Deterministic Family Structures (DFS) by axiomatizing some properties of the residual relation and the family relation on redexes in an Abstract Rewriting System. We present two proofs of the Relative Normalization Theorem, one for SDRSs for regular stable sets, and another for DFSs for all stable sets of desirable ‘normal forms’. We further prove the Relative Optimality Theorem for DFSs. We extend this result to deterministic Computation Structures which are deterministic Event Structures with an extra relation expressing self-essentiality.


haifa verification conference | 2005

Simultaneous SAT-Based model checking of safety properties

Zurab Khasidashvili; Alexander Nadel; Amit Palti; Ziyad Hanna

We present several algorithms for simultaneous SAT (propositional satisfiability) based model checking of safety properties. More precisely, we focus on Bounded Model Checking and Temporal Induction methods for simultaneously verifying multiple safety properties on the same model. The most efficient among our proposed algorithms for model checking are based on a simultaneous propositional satisfiability procedure (SSAT for short), which we design for solving related propositional objectives simultaneously, by sharing the learned clauses and the search. The SSAT algorithm is fully incremental in the sense that all clauses learned while solving one objective can be reused for the remaining objectives. Furthermore, our SSAT algorithm ensures that the SSAT solver will never re-visit the same sub-space during the search, even if there are several satisfiability objectives, hence one traversal of the search space is enough. Finally, in SSAT all SAT objectives are watched simultaneously, thus we can solve several other SAT objectives when the search is oriented to solve a particular SAT objective first. Experimental results on Intel designs demonstrate that our new algorithms can be orders of magnitude faster than the previously known techniques in this domain.


colloquium on trees in algebra and programming | 1994

On Higher Order Recursive Program Schemes

Zurab Khasidashvili

We define Higher Order Recursive Program Schemes (HRPSs) by allowing metasubstitutions (as in the λ-calculus) in right-hand sides of function and quantifier definitions. A study of several kinds of similarity of redexes makes it possible to lift properties of (first order) Recursive Program Schemes to the higher order case. The main result is the decidability of weak normalization in HRPSs, which immediately implies that HRPSs do not have full computational power. We analyze the structural properties of HRPSs and introduce several kinds of persistent expression reduction systems (PERSs) that enjoy similar properties. Finally, we design an optimal evaluation procedure for PERSs.


high level design validation and test | 2001

An enhanced cut-points algorithm in formal equivalence verification

Zurab Khasidashvili; John Moondanos; Daher Kaiss; Ziyad Hanna

BDD-based cut-points verification is widely used informal verification. The authors have recently developed a cut-points verification algorithm that is unique in that it avoids generation of false-negatives and allows simplification of the circuits to be compared based on reconvergence of input variables. Here we describe several refinements and enhancements that lead both to drastic speedup as well increase in capacity. These methods are already implemented in Intels combinational verifier CLEVER and show very promising results on real life examples from the pentium design family.


Information & Computation | 2001

Perpetuality and Uniform Normalization in Orthogonal Rewrite Systems

Zurab Khasidashvili; Mizuhito Ogawa; Vincent van Oostrom

We study perpetuality of reduction steps, as well as perpetuality of redexes, in orthogonal rewrite systems. A perpetual step is a reduction step which retains the possibility of infinite reductions. A perpetual redex is a redex which, when put into an arbitrary context, yields a perpetual step. We generalize and refine existing criteria for the perpetuality of reduction steps and redexes in orthogonal term rewriting systems and the ?-calculus due to Bergstra and Klop and others. We first introduce context-sensitive conditional expression reduction systems (CCERSs) and define a concept of orthogonality (which implies confluence) for them. In particular, several important ?-calculi and their extensions and restrictions can naturally be embedded into orthogonal CCERSs. We then define a perpetual reduction strategy which enables one to construct minimal (w.r.t. Levys permutation ordering on reductions) infinite reductions in orthogonal fully-extended CCERSs. Using the properties of the minimal perpetual strategy, we prove 1.perpetuality of any reduction step that does not erase potentially infinite arguments, which are arguments that may become, via substitution, infinite after a number of outside steps, and 2.perpetuality (in every context) of any safe redex, which is a redex whose substitution instances may discard infinite arguments only when the corresponding contracta remain infinite. We prove both these perpetuality criteria for orthogonal fully-extended CCERSs and then specialize and apply them to restricted ?-calculi, demonstrating their usefulness. In particular, we prove the equivalence of weak and strong normalization (whose equivalence is here called uniform normalization) for various restricted ?-calculi, most of which cannot be derived from previously known perpetuality criteria.


CTRS '94 Proceedings of the 4th International Workshop on Conditional and Typed Rewriting Systems | 1994

Relative Normalization in Orthogonal Expression Reduction Systems

John R. W. Glauert; Zurab Khasidashvili

We study reductions in orthogonal (left-linear and non-ambiguous) Expression Reduction Systems, a formalism for Term Rewriting Systems with bound variables and substitutions. To generalise the normalization theory of Huet and Levy, we introduce the notion of neededness with respect to a set of reductions π or a set of terms \(\mathcal{S}\) so that each existing notion of neededness can be given by specifying π or \(\mathcal{S}\). We imposed natural conditions on \(\mathcal{S}\), called stability, that are sufficient and necessary for each term not in \(\mathcal{S}\)-normal form (i.e., not in \(\mathcal{S}\)) to have at least one \(\mathcal{S}\)-needed redex, and repeated contraction of \(\mathcal{S}\)-needed redexes in a term t to lead to an \(\mathcal{S}\)-normal form of t whenever there is one. Our relative neededness notion is based on tracing (open) components, which are occurrences of contexts not containing any bound variable, rather than tracing redexes or subterms.


Electronic Notes in Theoretical Computer Science | 2003

SAT-Based Methods for Sequential Hardware Equivalence Verification without Synchronization

Zurab Khasidashvili; Ziyad Hanna

The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset state of a circuit is a hard problem. In this paper we propose a method allowing usage of SAT-based verification methods without a need for a user-given or a computed initial state. The idea is to employ a binary encoding of 3-valued modeling of circuits, and use the undefined state X as a reset state.


ALP '96 Proceedings of the 5th International Conference on Algebraic and Logic Programming | 1996

Discrete Normalization and Standardization in Deterministic Residual Structures

Zurab Khasidashvili; John R. W. Glauert

We prove a version of the Standardization Theorem and the Discrete Normalization Theorem in stable Deterministic Residual Structures, Abstract Reduction Systems with axiomatized notions of residual, which model orthogonal rewrite systems. The latter theorem gives a strategy for construction of reductions Levy-equivalent (or permutation-equivalent) to a given, finite or infinite, regular (or semi-linear) reduction, based on the neededness concept of Huet and Levy. This and other results of this paper add to the understanding of Levy-equivalence of reductions, and consequently, Levys reduction space. We demonstrate how elements of this space can be used to give denotational semantics to known functional languages in an abstract manner.

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