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international symposium on microarchitecture | 1992

The message-driven processor: a multicomputer processing node with efficient mechanisms

William J. Dally; J.A.S. Fiske; John S. Keen; Richard Lethin; Michael D. Noakes; Peter R. Nuth; R.E. Davison; G. Fyler

The message-driven processor (MDP), a 36-b, 1.1-million transistor, VLSI microcomputer, specialized to operate efficiently in a multicomputer, is described. The MDP chip includes a processor, a 4096-word by 36-b memory, and a network port. An on-chip memory controller with error checking and correction (ECC) permits local memory to be expanded to one million words by adding external DRAM chips. The MDP incorporates primitive mechanisms for communication, synchronization, and naming which support most proposed parallel programming models. The MDP system architecture, instruction set architecture, network architecture, implementation, and software are discussed.<<ETX>>


international conference on management of data | 1993

Performance evaluation of ephemeral logging

John S. Keen; William J. Dally

Ephemeral logging (EL) is a new technique for managing a log of database activity on disk. It does not require periodic checkpoints and does not abort lengthy transactions as frequently as traditional firewall logging for the same amount of disk space. Therefore, it is well suited for highly concurrent databases and applications which have a wide distribution of transaction lifetimes. This paper briefly explains EL and then analyzes its performance. Simulation studies indicate that it can offer significant savings in disk space, at the expense of slightly higher bandwidth for logging and more main memory. The reduced size of the log implies much faster recovery after a crash as well as cost savings. EL is the method of choice in some but not all situations. We assess the limitations of our current knowledge about EL and suggest promising directions for further research.


ACM Transactions on Database Systems | 1997

Extended ephemeral logging: log storage management for applications with long lived transactions

John S. Keen; William J. Dally

XEL segments a log into a chain of fixed-size FIFO queues and performs generational garbage collection on records in the log. Log records that are no longer necessary for recovery purposes are “thrown away” when they reach the head of a queue; only records that are still needed for recovery are forwarded from the head of one queue to the tail of the next. XEL does not require checkpoints, permits fast recovery after a crash and is well suited for applications that have a wide distribution of transaction lifetimes. Quantitative evaluation of XEL via simulation indicates that it can significantly reduce the disk space required for the log, at the expense of slightly higher bandwidth for log information and more main memory; the reduced size of the log permits much faster recovery after a crash as well as cost savings. XEL can significantly reduce both the disk space and the disk bandwidth required for log information in a system that has been augmented with a nonvolatile region of main memory.


international conference on computer design | 1992

The Message Driven Processor: an integrated multicomputer processing element

William J. Dally; Andrew A. Chien; J.A.S. Fiske; G. Fyler; Waldemar Horwat; John S. Keen; Richard Lethin; Michael D. Noakes; Peter R. Nuth; D.S. Wills

A description is given of the Message-Driven Processor (MDP), an integrated multicomputer node. It incorporates a 36-bit integer processor, a memory management unit, a router for a 3D mesh network, a network interface, a 4K*36-bit word static RAM (SRAM), and an ECC dynamic RAM (DRAM) controller on a single 1.1 M-transistor VLSI chip. The MDP is not specialized for a single model of computation. Instead, it incorporates efficient primitive mechanisms for communication, synchronization, and naming. These mechanisms support most proposed parallel programming models. Each processing node of the MIT J-Machine consists of an MDP with 1 Mbit of DRAM.<<ETX>>


international symposium on computer architecture | 1998

Retrospective: the J-machine

William J. Dally; Andrew A. Chien; Stuart Fiske; Waldemar Horwat; Richard Lethin; Michael D. Noakes; Peter R. Nuth; Ellen Spertus; Deborah A. Wallach; D. Scott Wills; Andrew Chang; John S. Keen

1 Computer Systems ’ Department of Computer 3 Department of Electrical Laboratory, Stanford Science, University of Illinois, and Computer Engineering, University Urbana-Champaign Georgia Institute of Technology 4 Netscape Communications 5 Equator Technologies 6 Hewlett Packard Consulting Laboratories 7 Department of Computer 8 DEC, Western Research 9 Silicon Graphics Computer Science, Mills College Laboratory Systems


Digest of Papers. Compcon Spring | 1993

The J-Machine architecture and evaluation

William J. Dally; John S. Keen; Michael D. Noakes

The authors discuss the architecture of the J-Machine and evaluate the effectiveness of the mechanisms embodied in the message-driven processor (MDP). The J-Machine is a fine-grained distributed memory multicomputer that provides low-overhead mechanisms for general-purpose parallel computing. Each processing node consists of an MDP and 1 Mbyte of DRAM. The MDP microprocessor integrates communication, computation, and memory management functions in a single VLSI chip. A 512-node J-Machine is operational and is due to be expanded to 1024 nodes in January 1993.<<ETX>>


Computing Systems in Engineering | 1992

The J-Machine: A fine-grain parallel computer

William J. Dally; Andrew A. Chien; R.E. Davison; J.A.S. Fiske; S. Furman; G. Fyler; D.B. Gaunce; Waldemar Horwat; S. Kaneshiro; John S. Keen; Richard Lethin; Michael D. Noakes; Peter R. Nuth; Ellen Spertus; Brian Totty; Deborah A. Wallach; D.S. Wills

Abstract Most modern computers, whether parallel or sequential, are coarse grained. They are composed of physically large nodes with tens of megabytes of memory. Only a small fraction of the silicon area in the machine is devoted to computation. By increasing the ratio of computation area to memory area, fine-grain computers offer the potential of improving cost/performance by several orders of magnitude. To efficiently operate at such a fine grain, however, a machine must provide mechanisms that permit rapid access to global data and fast interaction between nodes. The MIT J-Machine is a fine-grain concurrent computer that provides low-overhead mechanisms for parallel computing. Prototype J-Machines have been operational since July 1991. The J-Machine communication mechanism permits a node to send a message to any other node in the machine in μ s. On message arrival, a task is created and dispatched in μ s. A translation mechanism supports a global virtual address space. These mechanisms efficiently support most proposed models of concurrent computation and allow parallelism to be exploited at a grain size of 10 operations. The hardware is an ensemble of up to 65,536 nodes each containing a 36-bit processor, 4K 36-bit words of on-chip memory, 256K words of DRAM and a router. The nodes are connected by a high-speed three-dimensional mesh network.


conference on information and knowledge management | 1994

XEL: extended ephemeral logging for log storage management

John S. Keen; William J. Dally

Extended ephemeral logging (XEL) is a more general variation of the ephemeral logging (EL) technique for managing a log of database activity on disk; it does not require a timestamp to be maintained with each object in the database. XEL does not require periodic checkpoints and does not abort lengthy transactions as frequently as traditional firewall logging for the same amount of disk space. Therefore, it is well suited for concurrent databases and applications which have a wide distribution of transaction lifetimes. Simulation results indicate that XEL can offer significant savings in disk space, at the expense of slightly higher bandwidth for logging and more main memory. The reduced size of the log permits much faster recovery after a crash as well as cost savings.


ifip congress | 1989

The J-Machine: A Fine Grain Concurrent Computer

William J. Dally; Andrew A. Chien; Stuart Fiske; Waldemar Horwat; John S. Keen


Archive | 1992

The message-driven processor

William J. Dally; J.A.S. Fiske; John S. Keen; Richard Lethin; Michael D. Noakes; Peter R. Nuth; Robert Davison; G. Fyler

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Michael D. Noakes

Massachusetts Institute of Technology

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Waldemar Horwat

Massachusetts Institute of Technology

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Peter R. Nuth

Massachusetts Institute of Technology

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Richard Lethin

Massachusetts Institute of Technology

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Stuart Fiske

Massachusetts Institute of Technology

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J.A.S. Fiske

Massachusetts Institute of Technology

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Brian Totty

Massachusetts Institute of Technology

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