Waldemar Horwat

Architecture of a message-driven processor

We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.

Experience with CST: programming and implementation

CST is a programming language based on Smalltalk-802 that supports concurrency using locks, asynchronous messages, and distributed objects. In this paper, we describe CST: the language and its implementation. Example programs and initial programming experience with CST are described. Our implementation of CST generates native code for the J-machine, a fine-grained concurrent computer. Some compiler optimizations developed in conjunction with that implementation are also described.

The Message Driven Processor: an integrated multicomputer processing element

A description is given of the Message-Driven Processor (MDP), an integrated multicomputer node. It incorporates a 36-bit integer processor, a memory management unit, a router for a 3D mesh network, a network interface, a 4K*36-bit word static RAM (SRAM), and an ECC dynamic RAM (DRAM) controller on a single 1.1 M-transistor VLSI chip. The MDP is not specialized for a single model of computation. Instead, it incorporates efficient primitive mechanisms for communication, synchronization, and naming. These mechanisms support most proposed parallel programming models. Each processing node of the MIT J-Machine consists of an MDP with 1 Mbit of DRAM.<<ETX>>

Retrospective: the J-machine

1 Computer Systems ’ Department of Computer 3 Department of Electrical Laboratory, Stanford Science, University of Illinois, and Computer Engineering, University Urbana-Champaign Georgia Institute of Technology 4 Netscape Communications 5 Equator Technologies 6 Hewlett Packard Consulting Laboratories 7 Department of Computer 8 DEC, Western Research 9 Silicon Graphics Computer Science, Mills College Laboratory Systems

The J-Machine: A fine-grain parallel computer

Abstract Most modern computers, whether parallel or sequential, are coarse grained. They are composed of physically large nodes with tens of megabytes of memory. Only a small fraction of the silicon area in the machine is devoted to computation. By increasing the ratio of computation area to memory area, fine-grain computers offer the potential of improving cost/performance by several orders of magnitude. To efficiently operate at such a fine grain, however, a machine must provide mechanisms that permit rapid access to global data and fast interaction between nodes. The MIT J-Machine is a fine-grain concurrent computer that provides low-overhead mechanisms for parallel computing. Prototype J-Machines have been operational since July 1991. The J-Machine communication mechanism permits a node to send a message to any other node in the machine in μ s. On message arrival, a task is created and dispatched in μ s. A translation mechanism supports a global virtual address space. These mechanisms efficiently support most proposed models of concurrent computation and allow parallelism to be exploited at a grain size of 10 operations. The hardware is an ensemble of up to 65,536 nodes each containing a 36-bit processor, 4K 36-bit words of on-chip memory, 256K words of DRAM and a router. The nodes are connected by a high-speed three-dimensional mesh network.