John S. Seng

Reducing power with dynamic critical path information

Recent research has shown that dynamic information regarding instruction criticality can be used to increase microprocessor performance. Critical path information can also be used in processors to achieve a better balance of power and performance. This paper uses the output of a dynamic critical path predictor to decrease the power consumption of key portions of the processor without incurring a corresponding decrease in performance. The optimizations include effective use of functional units with different power and latency characteristics and decreased issue logic power.

Storageless value prediction using prior register values

This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce the value that is already stored in the destination register, we eliminate the need for large value buffers to enable value prediction. Even without the large buffers, register-value prediction can be made as or more effective than last-value prediction, particularly with the aid of compiler management of values in the register file.Both static and dynamic register value prediction techniques are demonstrated to exploit register-value reuse, the former requiring minimal instruction set architecture changes and the latter requiring a set of small confidence counters. We show an average gain of 12% with dynamic RVP and moderate compiler assistance on a next generation processor, and 15% on a 16-wide processor.

Power-sensitive multithreaded architecture

The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for single-thread architectures.

Robotics competition: Providing structure, flexibility, and an extensive learning experience

This paper presents the design and implementation of the annual robotics competition at Cal Poly State University, San Luis Obispo. Described are the infrastructure used to run the competition, the educational outcomes, and student responsibilities that make this competition an excellent opportunity for broad-based student educational growth. This annual robot competition provides a forum for students to receive educational credit while working on a multi-faceted project that provides an experience that is close to what they would encounter in their future professional career, and to compete for prizes. With faculty advisor supervision, the students have full responsibility for defining the competition rules, designing and constructing the competition course, developing partnerships with industry, and carrying out the competition. Each year the students define a new set of rules for the competition that results in the development of new robots. The key student learning possibilities that will be presented in the paper include: a) team-based learning; b) interdisciplinary experience that includes mechanical engineering and computer engineering; c) life-long learning skills; d) communication skills; e) leadership skills. Also this paper will address the key responsibilities of the faculty that are necessary for this student learning experience to be successful.

Experiences with the Blackfin architecture for embedded systems education

In the course of a major curriculum change at California Polytechnic State University, the embedded processing course was redesigned. During this process, the course had the opportunity to purchase new hardware. Analog Devices Black-fin processor was chosen based mostly on cost, but also on performance, development environment, and documentation. We first present our goals in the class. We then give an overview of the Blackfin architecture and how the Blackfin fits in with many of our goals. We then present the implementation of an expansion board developed to interface with Blackfins EZ-KIT Lite board. We present our experiences with this setup in the hopes that others who might be thinking of a similar curricular change can learn from our successes and failures. We outline the strengths and weaknesses of the Blackfin architecture as an educational platform, followed by a discussion of our experiences and a presentation of the support materials we developed to accompany the course, including lecture material and laboratories. Finally, we discuss our future directions for our uses with the board.

Semantically-enhanced information extraction

Information Extraction using Natural Language Processing (NLP) produces entities along with some of the relationships that may exist among them. To be semantically useful, however, such discrete extractions must be put into context through some form of intelligent analysis. This paper1,2 offers a two-part architecture that employs the statistical methods of traditional NLP to extract discrete information elements in a relatively domain-agnostic manner, which are then injected into an inference-enabled environment where they can be semantically analyzed. Within this semantic environment, extractions are woven into the contextual fabric of a user-provided, domain-centric ontology where users together with user-provided logic can analyze these extractions within a more contextually complete picture. Our demonstration system infers the possibility of a terrorist plot by extracting key events and relationships from a collection of news articles and intelligence reports.

Retrospective on “Power-Sensitive Multithreaded Architecture”

This article provides a retrospective look at the research that went into the 2000 ICCD paper “Power-Sensitive Multithreaded Architecture”. At the time, simultaneous multithreading processors were soon to be commercially available and power consumption was proving to be a challenging design constraint. That research introduced optimizations that increased power and energy efficiency through multithreading, while maintaining performance. This article discusses the optimizations in the paper and discusses how processor designs have changed since its publication.