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Featured researches published by John V. Oldfield.


ACM Sigarch Computer Architecture News | 1988

VLSI and rule-based systems

Peter M. Kogge; John V. Oldfield; Mark R. Brule; Charles D. Stormon

Many AI applications today employ some form of if-then rule-based programming. In languages stressing production rules, such as OPS, data is pattern matched against the if part until all literals are satisfied; the then part then indicates how the database should be changed. In more deductive languages like Prolog, the match is between a goal literal whose truth is unknown, and the then part of a rule. A successful match causes a series of goals from the if part to be solved in a similar manner.


international symposium on microarchitecture | 1992

A general-purpose CMOS associative processor IC and system

Charles D. Stormon; Nikos B. Troullinos; Edward M. Saleh; Abhijeet V. Chavan; Mark R. Brule; John V. Oldfield

An associative processor architecture that integrates the functionality of content-addressable memory (CAM), functional memory (FM), and associative parallel processors (APPs) in a single-chip architecture is described. The hardware design, environment and applications of the Coherent Processor, a microchannel memory device designed by combining 16 such chips, are discussed. It is shown that the processors writable control store permits quick execution of application-specific microcoded operations.<<ETX>>


IEEE Computer Graphics and Applications | 1983

A High-Level Recognizer for Schematic Diagrams

Douglas Tudhope; John V. Oldfield

This recognizer uses high-level knowledge stored in a global, modifiable database. It is adaptable to a variety of diagrams.


ACM Sigarch Computer Architecture News | 1994

Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities

Phil Allen; Franc Brglez; Hal Carter; Robert Caverly; Jerry Dillion; Albert Lo; Ron Lomax; John V. Oldfield; Cesar Pina; T. J. Wilkinson

Under sponsorship of the National Science Foundation, eleven participants from universities and industry and seven individuals from the NSF met during October 18-19, 1993, to assess the unique needs educators have for rapid prototyping of microelectronic systems and to suggest potential solutions for continuously improving the state-of-the-art in U.S. universities. The following vision statement was adopted: Educate students who can use the paradigm of design, simulate, design-for-test, build and test (as opposed to just design, build and test) to create microelectronic systems, not just integrated circuits tiCs), of sufficient quality that the global competitiveness of U.S. industry will be continued and enhanced. From this statement a number of findings and recommendations were made. Some of these include: (1) Student projects should be simulated thoroughly prior to submission to MOSIS for fabrication. (2) The use of Field-Programmable Gate Arrays (FPGAs) to support logic design and systems-oriented courses should be encouraged. (3) Fabrication services provided by MOSIS should be used largely for designs in which some portion has been performed manually. (4) NSF support for advanced classes should be broadened to include not only IC fabrication via MOSIS but also the acquistion of prototyping boards or multi-chip modules (MCMs) (5) Remote access via the Internet to expensive testers and prototyping systems should be made available. (6) MOSIS should add the following services: BiCMOS process, microelectro-mechanical post-processing, optoelectronic device fabrication and MCM prototyping. (7) A national clearinghouse should be supported to provide ready access by the educational community to existing and rapidly emerging resources that are presently dispersed. (8) Conferences, faculty enhancement short courses and newsletters should be supported to encourage widespread exchange of information.


eurographics | 1991

Content-Addressable Memories for Quadtree-Based Images

John V. Oldfield; Richard D. Williams; Neil E. Wiseman; Mark R. Brule

Quadtrees are attractive for storing and processing mages with area coherence, but performance has been limited by software overheads. A Content-Addressable Memory (CAM) with ternary storage allows single-cycle searches by pixel coordinate, quadrant or rectangle. To use thiS feature effectively the authors have reviewed a range of quadtree processing functions relevant to computer graphics and Image processing, and some new algorithms have been discovere. The proposed VLSI chip has microcoded logic on each row, as well as its CAM cells. This architecture has been simulated in fine detail with the aid of the Connection Machine as well as by much slower, conventional computers. The combination of quadtrees and CAMs offers significant improvement in performance for display systems and image processing.


Archive | 1994

Field-programmable gate arrays: reconfigurable logic for rapid prototyping and implementation of digital systems

John V. Oldfield; Richard C. Dorf


Electronics Letters | 1987

Content-addressable memories for storing and processing recursively subdivided images and trees

John V. Oldfield; R.D. Williams; N.E. Wiseman


international conference on lightning protection | 1988

An Architecture Based on Content-Addressable Memory for the Rapid Execution of Prolog.

Charles D. Stormon; Mark R. Brule; John V. Oldfield; D. F. Ribeiro


IEE Proceedings E Computers and Digital Techniques | 1989

Content-addressable memories applied to execution of logic programs

J.C.D.F. Ribeiro; Charles D. Stormon; John V. Oldfield; Mark R. Brule


Electronics Letters | 1993

Minimum spanning tree generation with content-addressable memory

T.G. Park; John V. Oldfield

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N.E. Wiseman

University of Cambridge

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