John W. M. Rogers

The effect of varactor nonlinearity on the phase noise of completely integrated VCOs

This work discusses variations in phase noise over the tuning range of a completely integrated 1.9-GHz differential voltage-controlled oscillator (VCO) fabricated in a 0.5-/spl mu/m bipolar process with 25-GHz f/sub t/. The design had a phase noise of -103 dBc/Hz at 100 kHz offset at the top of the tuning range, but the noise performance degraded to -96 dBc/Hz at 100 kHz at the bottom of the tuning range. It was determined that nonlinearities of the on-chip varactors, which led to excessively high VCO gain at the bottom of the tuning range, were primarily responsible for this degradation in performance. The VCO has a power output of -5 dBm per side. Calculations predict phase noise with only a small error and provide design insight for minimizing this effect. The oscillator core drew 6.4 mA and the output buffer circuitry drew 6 mA, both from a 3.3-V supply.

A fully integrated multiband MIMO WLAN transceiver RFIC

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.

A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators

This paper presents both analog and digital automatic-amplitude control techniques for voltage-controlled oscillators (VCOs). These feedback mechanisms help to keep the VCOs at an optimum amplitude over temperature, process, and voltage variations. The VCOs were fabricated in a 50-GHz SiGe BiCMOS process. They use MOS varactors and achieve a 600-MHz tuning range in the 2-GHz band. The phase noise of the VCO with analog control was measured to be -99 dBc/Hz at 100-kHz offset from the carrier. The digital loop allows for a more optimized VCO core that achieves a phase noise of -108.5 dBc/Hz at 100-kHz offset in a low-gain mode. Techniques for suppressing the phase noise in regions of high gain are also presented. The VCOs draw between 4 and 8 mA from a 3.3-V supply.

A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC

This work presents a shared fractional-N synthesizer used by two dual-band 802.11 radios integrated on a single chip for 2/spl times/2 multiple-input multiple-output (MIMO) applications. Additional 2/spl times/2 MIMO chips can be used in a system by phase synchronizing the signal paths through a bidirectional LO porting scheme developed for this application. This synthesizer was fully integrated with the exception of an off-chip loop filter. The synthesizer is a /spl Delta//spl Sigma/-based fractional-N frequency synthesizer with three on-chip LC tuned VCOs to cover the entire frequency bands specified in the IEEE 802.11a/b/g and Japanese WLAN standards. The radio uses a variable IF frequency so that both the RF LO and IF LO can be derived from a single synthesizer saving chip area and power. The synthesizer includes a programmable second/third-order /spl Delta//spl Sigma/ noise shaper, a phase frequency detector, a differential charge pump, and a 6-bit multimodulus divider (MMD). The nominal jitter from 100 Hz to 10 MHz is 0.63-0.86/spl deg/ rms in the 5-GHz band and 0.35-0.43/spl deg/ rms in the 2.4-GHz band. The maximum frequency deviation of the synthesizer when enabling the transmitter is less than 150 kHz and the frequency error settles to 2 kHz in less than 12 /spl mu/s. For MIMO applications requiring more than two full paths, a single synthesizer on one die can be used to generate the LOs for all other radios integrated in different dies.

Post-processed Cu inductors with application to a completely integrated 2-GHz VCO

A simple post-processing technique allowing Cu inductors to be added to integrated circuits fabricated in technologies providing only Al metallization is presented. The inductors use a 4-/spl mu/m thick electroless plated Cu layer to minimize resistance, and are formed over a 9-/spl mu/m thick polyimide dielectric to reduce substrate losses. Inductors optimized for 2.5-GHz had Q as high as 17. The effectiveness of the post-processing technique is demonstrated by application to a voltage-controlled oscillator (VCO) fabricated in a commercial bipolar technology with Al metallization. Circuits with post-processed Cu inductors gave a phase noise of -106 dBf/Hz at 100 kHz offset from a 2-GHz carrier, while control circuits with Al inductors gave a phase noise of only -101 dBc/Hz at 100 kHz offset from a 1.8-GHz carrier and had higher power consumption.

A 6.3 GHz BFSK Transmitter with On-Chip Antenna for Self-Powered Medical Sensor Applications

This paper presents a completely integrated, low-power 6.3 GHz oscillator transmitter which includes an on-chip antenna suitable for short-range medical sensor applications. The transmitter, implemented in a 1.2 V 0.13 mum CMOS process, utilizes open-loop direct VCO modulation for BFSK data at a rate of 300 kbps. For communicating a 1 kbit packet once per second, an average power consumption of 14 muW is achieved. During a packet transmission, the power consumption of the transmitter is 4.25 mW, enabling a self-powered design using integrated ultracapacitors for an SoC solution. With a radiated power of 0 dBm, the transmitter has a communication range of 2 m.

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.

A fully integrated multi-band MIMO WLAN transceiver RFIC

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.

A Fully Integrated 14 Band, 3.1 to 10.6 GHz 0.13 μm SiGe BiCMOS UWB RF Transceiver

A fully integrated WiMedia compliant UWB transceiver supporting band groups 1 to 6 (3.168 GHz to 10.560 GHz), implemented in 0.13 μm SiGe BiCMOS technology will be presented. The transceiver is packaged in a small 40 pin 5 mm × 5 mm micro lead frame (MLF) package and includes a broadband T/R switch, RF balun and all PLL loop filter components. The receiver has a NF of 4.5 dB to 5.8 dB and a dynamic range of more than 50 dB. The transmitter meets US and international transmit mask requirements.

A 5 GHz radio front-end with automatically Q tuned notch filter

Low voltage designs of front-end components for 5 GHz radio applications are presented. A notch filter with automatic Q tuning is integrated with the LNA to provide image rejection. On-chip transformers are used extensively in the receiver. The receiver had a gain of 19.8 dB, noise figure of 4.5 dB, an IIP3 of -11.5 dBm, and the VCO had a phase noise of -116 dBc/Hz at 1 MHz offset.