Foster F. Dai

A fully integrated multiband MIMO WLAN transceiver RFIC

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.

A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC

This work presents a shared fractional-N synthesizer used by two dual-band 802.11 radios integrated on a single chip for 2/spl times/2 multiple-input multiple-output (MIMO) applications. Additional 2/spl times/2 MIMO chips can be used in a system by phase synchronizing the signal paths through a bidirectional LO porting scheme developed for this application. This synthesizer was fully integrated with the exception of an off-chip loop filter. The synthesizer is a /spl Delta//spl Sigma/-based fractional-N frequency synthesizer with three on-chip LC tuned VCOs to cover the entire frequency bands specified in the IEEE 802.11a/b/g and Japanese WLAN standards. The radio uses a variable IF frequency so that both the RF LO and IF LO can be derived from a single synthesizer saving chip area and power. The synthesizer includes a programmable second/third-order /spl Delta//spl Sigma/ noise shaper, a phase frequency detector, a differential charge pump, and a 6-bit multimodulus divider (MMD). The nominal jitter from 100 Hz to 10 MHz is 0.63-0.86/spl deg/ rms in the 5-GHz band and 0.35-0.43/spl deg/ rms in the 2.4-GHz band. The maximum frequency deviation of the synthesizer when enabling the transmitter is less than 150 kHz and the frequency error settles to 2 kHz in less than 12 /spl mu/s. For MIMO applications requiring more than two full paths, a single synthesizer on one die can be used to generate the LOs for all other radios integrated in different dies.

A novel low-power input-independent MOS AC/DC charge pump

The paper presents a novel fully integrated MOS AC to DC charge pump with low power dissipation and stable output for RFID applications. To improve the input sensitivity, we replaced the Schottky-diodes in conventional charge pumps with MOS diodes with zero threshold, which have fewer process defects and are thus more compatible with other circuits. The charge pump in a RFID transponder is implemented in a 0.35 /spl mu/m CMOS technology with 0.24 mm/sup 2/ size. The analytical model of the charge pump and the simulation results are presented.

An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC

This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3 × 2.5 mm2. The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 GHz·2SFDR/6/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is - 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18

This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm2. The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.

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We present a built-in self-test (BIST) approach based on a direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. A main contribution of this paper is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) and frequency response, including both phase and gain. The approach has been implemented in Verilog and synthesized into a field-programmable gate array (FPGA), where it was used for functional testing of an actual device under test (DUT) and compared to simulation results

m SiGe BiCMOS Technology

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.

Automatic linearity and frequency response tests with built-in pattern generator and analyzer

This paper presents a 2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). A nonlinear current steering digital to analog converter (DAC) has been utilized to convert phase word to sine wave amplitude directly without area consuming ROM for the sine look-up table, which is the speed bottleneck of the DDFS circuit. In order to achieve high speed performance and low power dissipation, CMOS current mode logic (CML) is chosen to implement the logic cells. A semi-symmetrical switching scheme of current source matrix of the nonlinear DAC is proposed to compensate the systematic and gradient errors introduced by the processing and environment variations. The DDFS chip is implemented in Chartered 0.35 /spl mu/m CMOS technology with die area of 2.1/spl times/1.9 mm/sup 2/ and total power consumption of 820 mW at 3.3 V supply voltage.

A fully integrated multi-band MIMO WLAN transceiver RFIC

We present a built-in self-test (BIST) approach, based on a direct digital synthesizer (DDS), for functional test of analog circuitry in mixed-signal systems. DDS with delta-sigma noise shaping is used to generate test signals with different frequencies and phases. The DDS-based BIST hardware implementation can sweep the frequencies through the interested bands and thus measure the frequency response of the analog circuit. The proposed BIST approach has been implemented in Verilog and synthesized into a field programmable gate array (FPGA). The actual device under test (DUT) was implemented using a field programmable analog array (FPAA) to form a complete BIST testbed for analog functional tests.

2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer

This paper presents an 80-MHz 12-bit cryogenic low-power digital-to-analog converter (DAC) implemented in a 0.5-mum SiGe BiCMOS technology. The cryogenic DAC is capable of operating over an ultrawide temperature (UWT) ranging from -180degC to +120degC and under the high-energy particle radiation environment on the lunar surface. A bandgap voltage reference for the UWT applications is designed using SiGe heterojunction bipolar transistors, and the current-steering DAC is implemented using a segmented current source array. The design considerations for both extreme temperature and radiation environments are discussed. The cryogenic and radiation-tolerant DAC chip occupies a die area of 3.5 times 1.8 mm2 and consumes only 39.6 mW from a 3.3-V supply voltage. The maximum DAC sampling rate was measured at 80 MS/s at -180degC using a 40-pin dual in-line package.