John W. Stoughton

Prediction of performance and processor requirements in real-time data flow architectures

Presents a new data flow graph model for describing the real-time execution of iterative control and signal processing algorithms on multiprocessor data flow architectures. Identified by the acronym ATAMM, for Algorithm to Architecture Mapping Model, the model is important because it specifies criteria for a multiprocessor operating system to achieve predictable and reliable performance. Algorithm performance is characterized by execution time and iteration period. For a given data flow graph representation, the model facilitates calculation of greatest lower bounds for these performance measures. When sufficient processors are available, the system executes algorithms with minimum execution time and minimum iteration period, and the number of processors required is calculated. When only limited processors are available or when processors fail, performance is made to degrade gracefully and predictably. The user off-line is able to specify tradeoffs between increasing execution time or increasing iteration period. The approach to achieving predictable performance is to control the injection rate of input data and to modify the data flow graph precedence relations so that a processor is always available to execute an enabled graph node. An implementation of the ATAMM model in a four-processor architecture based on Westinghouses VHSIC 1750A Instruction Set Processor is described. >

Strategies for predictability in real-time data-flow architectures

Consideration is given to the development of strategies for predictable performance in homogeneous multicomputer data-flow architectures operating in real-time. Algorithms are restricted to the class of large-grained, decision-free algorithms. The mapping of such algorithms onto the specified class of data-flow architectures is realized by a new marked graph model called ATAMM (algorithm to architecture mapping model). Algorithm performance and resource needs are determined for predictable periodic execution of algorithms, which is achieved by algorithm modification and input data injection control. Performance is gracefully degraded to adapt to decreasing numbers of resources. The realization of the ATAMM model on a VHSIC four processor testbed is described. A software design tool for prediction of performance and resource requirements is described and is used to evaluate the performance of a space surveillance algorithm.<<ETX>>

Modeling and performance bounds for concurrent processing

A novel graph-theoretic model for describing the relation between a decomposed algorithm and its execution in a multiprocessor environment is developed. Called ATAMM, the model consists of a set of Petri-net marked graphs that incorporates the general specifications of a data-flow architecture. The model is useful for representing decision-free algorithms having large-grained, computationally complex primitive operations. Performance measures of computing speed and throughput capacity are defined. The ATAMM model is used to develop analytically lower bounds for these parameters.<<ETX>>

Fetal heart rate estimation via adaptive least mean square linear prediction methods

Adaptive signal processing methods are presented in support of a noninvasive ambulatory fetal heart rate monitor. Adaptive least mean square (LMS) linear prediction methods are used for fetal heart tone signature analysis and detection in the presence of background acoustic noise. The signal processing techniques designed to identify, analyze, and detect the fetal phonocardiographic signature are discussed. Subsequent evaluation of the detected fetal heart tone events are used to determine the instantaneous heart rate. Preliminary investigation has indicated that linear prediction is feasible for detecting the fetal heart tones in an advanced acoustic fetal heart rate monitor. A prediction length of eight was found to be suboptimal in minimizing the total mean square error over the training event.<<ETX>>

Analysis tool for concurrent processing computer systems

Diagnostics software for analyzing ATAMM (algorithm-to-architecture-mapping) based concurrent processing is presented. ATAMM is a Petri-net-based model capable of modeling the execution of computationally complex algorithms on distributed data-flow architectures. The ATAMM multicomputer operating system (AMOS), which enforces the ATAMM rules for predictable multiprocessing, is presented. The software presented referred to as the analysis tool, evaluates the behavior and performance of an ATAMM-based system by examining the time-tagged AMOS communication events collected in a file during execution. The tool provides automatic and user-interactive measurements of throughput, concurrency, resource utilization, and system overhead. The analysis-tool capabilities are demonstrated by evaluating the simulated execution of a specific algorithm graph for a given set of operating system parameters. Measurements of throughput and overhead are used to assess the effect of the operating system on ideal performance.<<ETX>>

Performance modeling for the ATAMM data flow architecture

The algorithm-to-architecture mapping model (ATAMM) is a new marked graph (a class of Petri net) model from which the rules for data and control flow in a homogeneous, multicomputer, data-flow architecture may be defined. This study is concerned with performance modeling for periodic execution of large-grain, decision-free algorithms in such an ATAMM-defined architecture. Major applications are expected to be real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The computing environment, problem domain, and algorithm execution pattern are described. Performance measures of computing speed and throughout capacity are defined. Performance bounds are established. Resource (computing element) needs are determined for periodic execution of algorithms.<<ETX>>

A design tool for computations in large grain real-time data flow architectures

A design tool for performance prediction in homogeneous, multicomputer dataflow architectures operating in real time is discussed. Algorithms are restricted to the class of large-grain, decision-free algorithms. Major applications are expected to be real-time implementation of control and signal processing algorithms, where performance is required to be highly predictable. The mapping of such algorithms onto the specified class of dataflow architectures is realized by a marked graph model called the algorithm to architecture mapping model (ATAMM). Performance measures which determine computing speed and throughput capacity are defined, and the lower bounds for these performance measures are stated. Computing resource needs are determined for predictable periodic execution of algorithms. A software design tool is presented to aid the designer in predicting performance and resource requirements.<<ETX>>

Further results in Walsh domain filtering

Zarowski and Yunik [1] demonstrated that an FIR filter can be realized with fewer multiplications in the fast Walsh transform (FWT) domain than in the fast Fourier transform (FFT) domain for some transform lengths. This correspondence investigates the symmetry and sparseness of the Walsh gain matrices. An efficient sparse matrix algorithm is used to calculate the Walsh gain matrix.

Performance modeling and enhancement in real-time data flow architectures

The authors are concerned with performance modeling and enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures operating in real-time. The mapping of real-time algorithms onto data flow architectures is realized by a marked graph model called ATAMM (algorithm to architecture mapping model). Applications include control, surveillance, and signal processing problems. Performance is characterized by computing speed and throughput. Bounds on performance measures are established. A technique for transforming an algorithm to improve throughput while maintaining input-output equivalence is presented. The state equations of a linear time invariant system are modified to illustrate the throughput enhancement technique.<<ETX>>