Jon A. Casey

Development of a 50mm dual Flip Chip Plastic Land Grid Array package for server applications

For many years, the Flip Chip Plastic Ball Grid Array (FC-PBGA) has been the preferred packaging solution for microprocessors and high performance ASICs. IBM has developed a dual chip Flip Chip Plastic Land Grid Array (FC- PLGA) package to support low and mid range server solutions. This organic 50 mm times 50 mm lead reduced package solution uses a 6-4-6 build-up laminate with two large chips consisting of a processor (22 times 16 mm) and a memory cache (15 times 13 mm) in a single piece lid capping solution. In this paper, we will summarize development activities performed in order to achieve a reliable product while dissipating up to 200 Watts mostly from the microprocessor chip. One of the many key issues to overcome was the assurance of good package thermal stability with such large silicon area coverage over the flexible organic chip carrier. Special chip and module test vehicles were designed and fabricated in order to evaluate the mechanical, electrical, and thermal behaviour of the package post assembly and throughout stress testing. The assembly process development activities performed to support the desired application will be discussed in conjunction with mechanical modeling results. In addition, thermal data will be presented showing the positive results obtained as well as good correlation to the thermal and mechanical models.

Chip cracks during assembly: Finding and eliminating the critical defect

During the bond and assembly process of an organic module, the backside of the chip will be in tensile stress. Vertical cracking through the Silicon chip (as shown in Figure 1) can occur when the strength of the chip is lower than the stress that is applied through the bond and assembly processes and associated materials.

Green initiative-power management and its effects on electronics packaging

The influence of Green initiatives and resulting reduction in power consumption have an impact on module reliability. In this paper we will discuss an approach that IBM is using to acquire and save cyclic field data from processors as well as the testing methodology used to quantify the reliability impacts of variable cyclic loads on FCPLGA packages. Important questions to be answered are: (1) what types of cyclic loads will IBM modules see in the field as a result of power management and applications run by our diverse customer set, and (2) what unique testing must be conducted to assure that there is no reliability exposure associated with said cyclic loads. This paper discusses new failure mechanisms found through minicycle stressing in a lab environment, meant to simulate cyclic loads that a processor would see in the field, where power was being throttled to control overall consumption. We will also discuss the methodology and implementation of a Figure of Merit algorithm which allows us to pull cyclic load histories on individual processors while in the field or from processors that have been returned to IBM.

Electrical repair of multilayer ceramic (MLC) substrates

Ah st ract Electrically dcfcctive multilayer ceramic (MLC) substrates have historically been rcpaired using two primal?; methodolog~cs. both of \sldch have limitations Ilrat prevent thcir usage in new, high-performancc, MCM applications. A new repair mclhodolp has been developed whch utilizes pre-designed: spare internal nets within the substrate. Using new technology elements. a repair process has been developed whicli can isolate a defective net from within the substrate and then pmvidc a means to reconnect the clup interconnect (C1) to a spare net, rebuilding the electrical path.