Jennifer Muncy

Qualification of low-k 90nm technology dies with Pb-free bumps on a build-up laminate package (PBGA) with Pb-free assembly processes

Flip-chip packages have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic ball grid array (BGA) connections. Recently, there has been a significant focus on Pb-free packages to meet European Union mandated RoHS guidelines with exemptions allowed for server and other networking hardware. Towards this goal, IBM has been actively developing and qualifying Pb-free and Pb-reduced packages that cover the range of advanced semiconductor technologies such as 130nm and 90nm ground rules. In addition, for device performance reasons, the BEOL wiring layers on the high-performance 90nm wafers also require low-k dielectric materials. Finally, due to tighter wiring ground rules and faster device performance requirements, the build-up laminate packages require thin-core (400 micron) and advanced wiring pitch in the build-up layers. IBM has partnered with Amkor Technology to qualify both 130nm and 90 nm devices with Amkor developed Pb-free bumps using large die and build-up laminates. The die size used is ~15mm and the laminate qualified is 42.5mm with 1mm pitch Pb-free BGA. The bump pitch is 200micron. In this paper, we summarize the Sn/Ag Pb-free plated bumps that have been qualified for low-k 90nm technology on thin-core build-up laminates. Optimizations required for underfill material compatible with Pb-free bumps and low-k die are reviewed. Finally, high speed devices generate a significant amount of power, and an optimum thermal solution for FC-PBGA package is essential. Summary of package-level thermal performance is presented

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

Optimization of post Cu CMP cleaning performance can be accomplished through dilution ratio tuning and pad rinse of clean chemicals. Excessive chemical etching as well as megasonic power can induce high Cu roughness. Generation of hollow metal and Cu dendrite defects depends not only on the clean chemistry but also the queue time between plating and anneal and between CMP and cap. AFM and XPS provide insights into the cleaning mechanism. EM and TDDB tests are the ultimate tests for the effectiveness of post Cu CMP cleaning.

Development of a 50mm dual Flip Chip Plastic Land Grid Array package for server applications

For many years, the Flip Chip Plastic Ball Grid Array (FC-PBGA) has been the preferred packaging solution for microprocessors and high performance ASICs. IBM has developed a dual chip Flip Chip Plastic Land Grid Array (FC- PLGA) package to support low and mid range server solutions. This organic 50 mm times 50 mm lead reduced package solution uses a 6-4-6 build-up laminate with two large chips consisting of a processor (22 times 16 mm) and a memory cache (15 times 13 mm) in a single piece lid capping solution. In this paper, we will summarize development activities performed in order to achieve a reliable product while dissipating up to 200 Watts mostly from the microprocessor chip. One of the many key issues to overcome was the assurance of good package thermal stability with such large silicon area coverage over the flexible organic chip carrier. Special chip and module test vehicles were designed and fabricated in order to evaluate the mechanical, electrical, and thermal behaviour of the package post assembly and throughout stress testing. The assembly process development activities performed to support the desired application will be discussed in conjunction with mechanical modeling results. In addition, thermal data will be presented showing the positive results obtained as well as good correlation to the thermal and mechanical models.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

Capacitors on organic modules: a new THB failure mode and method of detection

Multi-terminal low inductance capacitors (MTLICs) are used widely throughout the electronics industry to aid with voltage noise suppression and to manage high speed switching currents. They are implemented on system level cards as well as microprocessors and ASICs. MTLIC component dimensions are getting smaller with increased requirements on capacitance/inductance, driving more Ni plates (up to ∼160), thinner dielectrics and therefore resulting in an increased risk for failure in temperature, humidity and bias stressing. Traditionally, MTLICs have been more robust than the modules they are used on - but this may be changing.

Green initiative-power management and its effects on electronics packaging

The influence of Green initiatives and resulting reduction in power consumption have an impact on module reliability. In this paper we will discuss an approach that IBM is using to acquire and save cyclic field data from processors as well as the testing methodology used to quantify the reliability impacts of variable cyclic loads on FCPLGA packages. Important questions to be answered are: (1) what types of cyclic loads will IBM modules see in the field as a result of power management and applications run by our diverse customer set, and (2) what unique testing must be conducted to assure that there is no reliability exposure associated with said cyclic loads. This paper discusses new failure mechanisms found through minicycle stressing in a lab environment, meant to simulate cyclic loads that a processor would see in the field, where power was being throttled to control overall consumption. We will also discuss the methodology and implementation of a Figure of Merit algorithm which allows us to pull cyclic load histories on individual processors while in the field or from processors that have been returned to IBM.

Multi-terminal low inductance capacitor delamination failure

The following details a new test methodology offered as a cost effective alternative to module form-factor testing for detecting the delamination fail mode observed in Multiterminal low inductance capacitors (MTLICs) under temperature humidity bias (THB) reliability stress testing. This MTLIC test methodology yields the same delamination reliability failure-mode as observed in the module form-factor. We draw on this new testing methodology to highlight the influence of packaging materials, module form factor and component supplier on THB reliability performance of MTLIC components.