Jon T. Butler

Multiple-valued logic

The ultimate usefulness of a number system depends on its implementation. Multiple-valued logic has been implemented in charge-coupled devices (CCD). In this technology, logic values are encoded as charge. For example, prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland). Hitachi has implemented a 16-valued memory that stores the equivalent of 10/sup 6/ bits. CCD is more compact than any other VLSI technology. Although it is slower than CMOS (complementary metal oxide semiconductor), it is much faster than the disk and has the potential of replacing the disk. The use of multiple-valued logic in CCD increases its storage capacity significantly. Multiple-valued logic has also been implemented in current-mode CMOS. >

A method to represent multiple-output switching functions by using multi-valued decision diagrams

Multiple-output switching functions can be simulated by multiple-valued decision diagrams (MDDs) at a significant reduction in computation time. analyze the following approaches to the representation problem: shared multiple-valued decision diagrams (SMDDs), multi-terminal multiple-valued decision diagrams (MTMDDs), and shared multi-terminal multiple-valued decision diagrams(SMTMDDs). For example, we show that SMDDs fend to be compact, while SMTMDDs tend to be fast. We present an algorithm for grouping input variables and output functions in the MDDs.

Numerical Function Generators Using LUT Cascades

This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA)

A design method for look-up table type FPGA by pseudo-Kronecker expansion

In FPGA design, interconnections are often more expensive than logic. FPGAs using 3-input lookup tables (LUTs) require many logical levels and complex interconnections. On the other hand, FPGAs using 6-input LUTs require fewer interconnections and fewer logical levels. We show a method to represent logic functions by using pseudo-Kronecker diagrams (PKDDs). Experimental results show that 2-valued PKDDs require 29% fewer nodes than BDDs, and 4-valued PKDDs require 23% fewer than QDDs, the 4-valued extension of BDDs. Thus, this method is useful for the design of FPGAs with 6-input LUTs. However, when LUTs have less than 6-inputs, this method is not applicable.<<ETX>>

HAMLET-an expression compiler/optimizer for the implementation of heuristics to minimize multiple-valued programmable logic arrays

A description is given of HAMLET, a CAD tool written in C, that translates a user specification of a multiple-valued expression into a layout of a multiple-valued programmable logic array (MVL-PLA) which realizes that expression. It is modular to accommodate future minimization heuristics and future MVL-PLA technologies. At present, it implements two heuristics and one MVL-PLA technology, current-node CMOS. Specifically, HAMLET accepts a sum-of-products expression from the user, applies a minimization heuristic, and then produces a PLA layout of a multiple-valued current-mode CMOS PLA. In addition to its design capabilities, HAMLET can analyze heuristics. Random functions can be generated, heuristics applied, and statistics computed on the results. User-derived expressions can also be analyzed. In addition to the minimization heuristics, HAMLET can apply search strategies based on these heuristics, which, in the extreme, are exhaustive, producing true minimal forms.<<ETX>>

Minimization algorithms for multiple-valued programmable logic arrays

The authors compare the performance of three heuristic algorithms for the minimization of sum-of-products expressions realized by the H.G. Kerkhoff and J.T. Butlers (1986) multiple-valued programmable logic arrays. Heuristic methods are important because exact minimization is extremely time-consuming. The authors compare the heuristics to the exact solution, showing that heuristic methods are reasonably close to minimal. They use as a basis of comparison the average number of product terms over a set of randomly generated functions. All three heuristics produce nearly the same average number of product terms. Although the averages are close, there is surprisingly little overlap among the set of functions for which the best realization is achieved. Thus, there is a benefit to applying different heuristics and then choosing the best realization.<<ETX>>

Structural computer-aided design of current-mode CMOS logic circuits

A set of CAD (computer-aided design) tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based on the cost-table method. The general circuit structure, the cost-table functions, and the decomposition procedure used in the synthesis program are explained. The program is based on a logically complete set of basic elements for CMCL circuits. After circuit synthesis, the actual layout is generated using standard-cell IC design tools.<<ETX>>

Planar multiple-valued decision diagrams

In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2) symmetric functions, and 3) monotone increasing functions that produce planar decision diagrams. Our results apply to binary functions, as well. For example, we show that all two-valued monotone increasing threshold functions of up to five variables have planar binary decision diagrams.

The design of current mode CMOS multiple-valued circuits

A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizations that are almost as good. A cost-table that results in better realizations than obtained with a previous cost-table is proposed.<<ETX>>

Analysis of minimization algorithms for multiple-valued programmable logic arrays

The authors compare the performance of three heuristic algorithms for the minimization of sum-of-products expressions realized by the H.G. Kerkhoff and J.T. Butlers (1986) multiple-valued programmable logic arrays. Heuristic methods are important because exact minimization is extremely time-consuming. The authors compare the heuristics to the exact solution, showing that heuristic methods are reasonably close to minimal. They use as a basis of comparison the average number of product terms over a set of randomly generated functions. All three heuristics produce nearly the same average number of product terms. Although the averages are close, there is surprisingly little overlap among the set of functions for which the best realization is achieved. Thus, there is a benefit to applying different heuristics and then choosing the best realization. >