Jonas Fritzin

A Review of Watt-Level CMOS RF Power Amplifiers

This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched watt-level PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

Design and Analysis of a Class-D Stage With Harmonic Suppression

This paper presents the design and analysis of a low-power Class-D stage in 90 nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverter-based output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900 MHz, the measured output power was +5.1 dBm with drain efficiency (DE) and power-added efficiency (PAE) of 73% and 59% at 1.2 V. The 3rd and 5th harmonics were suppressed by 34 dB and 4 dB, respectively, compared to an inverter-based Class-D stage.

Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS

This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the model estimation problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluated for 5 MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to one of the first fully integrated +30 dBm Class-D outphasing RF PAs in 65 nm CMOS. At 1.95 GHz for a 5.5 V (6.0 V) supply voltage, the measured output power of the PA was +29.7 dBm (+30.5 dBm) with a power-added efficiency (PAE) of 27%. For the WCDMA signal with +26.0 dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5 MHz and 10 MHz offsets were - 46.3 dBc and - 55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3 dBm of channel power, the measured ACLR at 5 MHz offset was - 43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS

This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3rd harmonic and reduces the 5th harmonic. The technique creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2nd to 4th harmonics are measured to be −37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.

Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS

This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4–21.5dBm of output power with drain efficiencies and power-added efficiencies of 56–64% and 46–51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V, the output power dropped about 0.7dB.

Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS

This paper presents the design of two low- voltage differential class-E power amplifiers (PA) for DECT and Bluetooth fabricated in 130 nm CMOS. In order to minimize the on-chip losses and to achiev ...

Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN

This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.

Linearity, intermodulation distortion and ACLR in outphasing amplifiers

The distortion from amplitude and phase imbalance in outphasing amplifiers is discussed. The relation between dynamic range (DR) and suppression of distortion is shown to approximately follow a simple linear relationship depending on the DR. Approximate relations between adjacent channel leakage power ratio (ACLR) for different kinds of commonly used communication signals and two-tone intermodulation distortion are given. Relations between loss in output power and reduction of DR as functions of duty cycle in switching-based outphasing amplifiers are also given. An approximate method to evaluate the possible performance of digital pre-distortion (DPD) is also given by considering a DPD capable of correcting all distortions except amplitude imbalance. The predicted performance is compared to the performance obtained using a DPD-model found in the literature. The results show that the method is in good agreement, demonstrating that the proposed method can be used for design and evaluation of predistorted outphasing amplifiers.

A 72.2Mbit/s Transformer-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN

This paper describes the design of a power amplifier (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick-gate oxide (5.2 nm) transistors and a two-stage differential configuration with two integrated transformers for input and interstage matching. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 dBm and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

Behavioral modeling of outphasing amplifiers considering memory effects

This paper proposes a behavioral model structure for outphasing amplifiers. The model performance is evaluated on a class-D CMOS outphasing amplifier and compared with two models found in the literature. The proposed model structure also allows the use of memory in a parallel Hammerstein-like setting. The proposed models show improvements in adjacent channel error power ratio (ACEPR) of approximately 5 dB in addition to being linear in the parameters. The lower model errors enable the use and design of improved predistorters taking frequency dependency (memory effects) in outphasing amplifiers into account.