Jerzy Dabrowski

Mixed loopback BiST for RF digital transceivers

In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generator and response analyzer. The test is oriented at spot defects in a transceiver front-end. Estimates for noise, signal power and nonlinear distortions such as EVM (or SER), gain and IP3, respectively, are considered the test responses. Limitations of these tests are investigated with respect to the test path properties, the strength of defects and circuit tolerances. The IP3 test complements the EVM (SER) and gain tests for some spot defects. The analysis is verified by simulation of a functional-level RF transceiver model implemented in Matlab/spl trade/.

BiST model for IC RF-transceiver front-end

In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach.

A 1.4V 25mW Inductorless Wideband LNA in 0.13/spl mu/m CMOS

A 1.4V wideband inductorless LNA, implemented in a 0.13mum CMOS process, consumes 25mW and occupies 0.019mm2. Measurement results show 17dB voltage gain, 7GHz BW, 2.4dB NF at 3GHz, -4.1 dBm IIP3, and -20dBm P1dB. A common-drain feedback circuit provides wideband 50Omega input matching and partial noise cancellation. A current reuse technique improves both gain and power.

Built-in Loopback Test for IC RF Transceivers

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like bit error rate, error vector magnitude, or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. This paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

CMOS RF/DC Voltage Detector for on-Chip Test

In this paper we present a framework for RF testing of a radio front-end using CMOS RF/DC voltage detectors connected between RF nodes and a DC test bus. The detector is designed and implemented in 0.13mum CMOS process and it achieves high input impedance, low power, small area and wide dynamic range. Measurement results show that internal RF nodes can be accessed without significantly degrading the chip performance. A verification procedure using an extra DC bus is proposed to verify that due to process variations all detectors are within an acceptable performance limit.

Offset Loopback Test For IC RF Transceivers

In this paper we develop an offset loopback test setup for integrated RF transceivers (TRxs). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRxs). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade

Techniques for sensitizing RF path under SER test

This work presents two techniques for sensitizing the RF loopback path for an integrated transceiver under SER test. The test aims at spot defects typical of the CMOS process. At the chip level the spot defects are represented by impairments in gain and/or noise figure. The sensitization is based on SNR control of the test stimulus or on using a tuned interferer. In both cases power level control is crucial. The discussion is supported by simulation experiments.

Dual Band Tunable LNA for Flexible RF Front End

This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

LNA design for on-chip RF test

In this paper we present two CMOS LNA blocks designed for integration with other RF frontend blocks for on-chip test. Both of them are variants of the source degenerated LNA with embedded switches and/or a multiplexer, optimized with respect to their function and location. We discuss their functionality and performances in terms of test mode and the normal operation mode. The circuits are designed for 0.35mum CMOS process. Simulation results obtained at 2.4 GHz frequency, show a tradeoff between performance and testability. Nevertheless, the LNA circuit, which only uses embedded switches, proves a satisfactory design

Lookback BiST for RF front-ends in digital transceivers

This paper addresses a built-in self-test (BiST) for ICs digital transceivers. The focus is on testing the RF front-end while taking advantage of the on-chip DSP resources and DA-, and AD converters. The loopback architecture is used to preserve the sensitive RF blocks from extra noise and external disturbances. The test aims at spot defects typical of RF CMOS ICs, where those faults are deemed the main yield limiter in mass production. The fault model is discussed at three levels of design abstraction: layout, circuit and functional block. The BiST model is verified at the circuit and functional level. As a demonstrator a GSM transceiver model with loopback BiST is presented that provides a promising result.