Jonas Zürcher

Nanoparticle assembly and sintering towards all-copper flip chip interconnects

The current feed capability of typical flip chip electrical interconnects is constrained by the solder alloy, as it is more susceptible to electromigration than the copper used for the pads and wires. Hence, interconnects formed by copper only mitigate the electromigration risk and/or allow to increase the current limit of the all-copper interconnect. In this work, two methods to form all-copper flip chip interconnects at an annealing temperature of 250 °C are presented. The interconnects in the contact region between Cu pillars and Cu pads with a pitch down to 150 μm are formed by Cu nanoparticle self-assembly and sintering. In the first method, the entire gap between a Cu pillar chip and a substrate was filled with a Cu nano-suspension. The formation of capillary bridges during the evaporation of the dispersant directed the self-assembly of the nanoparticles towards the contact region between Cu pillars and Cu pad. In the second method, the Cu pillar chip was dipped into a film of the Cu nano-suspension, followed by a transfer, placement and release with a die bonder onto pads on a substrate. The annealing of the Cu nanoparticles is performed in both cases in a reducing formic acid atmosphere. The first method was more susceptible to the formation of shorts between pillars, whereas the second method resulted in electrical functional chip to substrate assemblies. Interconnects with a mean electrical resistance of 26 ± 3 mΩ and a shear strength ranging from 4.6 to 12.3 MPa were achieved. The sintered Cu nanoparticles bridged gaps up to 10 μm between copper pillars and pads, demonstrating the potential to apply the joint also on non-planar substrates. Nevertheless, imperfections such as voids and cracks are still present in the joints and need further process development, to improve the quality and process robustness further.

Steady-state low thermal resistance characterization apparatus: The bulk thermal tester

The reliability of microelectronic devices is largely dependent on electronic packaging, which includes heat removal. The appropriate packaging design therefore necessitates precise knowledge of the relevant material properties, including thermal resistance and thermal conductivity. Thin materials and high conductivity layers make their thermal characterization challenging. A steady state measurement technique is presented and evaluated with the purpose to characterize samples with a thermal resistance below 100 mm(2) K/W. It is based on the heat flow meter bar approach made up by two copper blocks and relies exclusively on temperature measurements from thermocouples. The importance of thermocouple calibration is emphasized in order to obtain accurate temperature readings. An in depth error analysis, based on Gaussian error propagation, is carried out. An error sensitivity analysis highlights the importance of the precise knowledge of the thermal interface materials required for the measurements. Reference measurements on Mo samples reveal a measurement uncertainty in the range of 5% and most accurate measurements are obtained at high heat fluxes. Measurement techniques for homogeneous bulk samples, layered materials, and protruding cavity samples are discussed. Ultimately, a comprehensive overview of a steady state thermal characterization technique is provided, evaluating the accuracy of sample measurements with thermal resistances well below state of the art setups. Accurate characterization of materials used in heat removal applications, such as electronic packaging, will enable more efficient designs and ultimately contribute to energy savings.

Enhanced centrifugal percolating thermal underfills based on neck formation by capillary bridging

We present a methodology for the formulation of percolating thermal underfills (PTUFs) with enhanced thermal conductivity for efficient heat dissipation between dies in 3D chip stacks. The methodology is based on the centrifugal filling of micron-sized powders in a confined space (defined by a solder ball array) to form a percolating particle bed, and on the formation of enhanced thermal contacts between particles and contacting surfaces, through the directed self-assembly of nanoparticles around the contacts (i.e. neck formation). The resulting composite material is characterized in terms of the fill fraction and its corresponding thermal conductivity with and without the formation of enhanced particle contacts. For underfills (UFs) formulated without enhanced contacts and using boron nitride, graphite or diamond powders, we have found thermal conductivity values ranging from 1.8 to 2.5 ± 0.1 W/m-K. The formation of enhanced particle contacts using silver nanoparticles dispensed in a 4.8 vol% suspension further increases the thermal conductivity to 3.8 ± 0.3 W/m-K; representing an increase of nearly one order of magnitude compared to silica laden capillary underfills (i.e. ~ 0.4 W/m-K). The thermal conductivity of all samples was measured using our in-home thermal conductivity tester. The increase in the thermal conductivity is related to thermal percolation resulting from the very high volumetric fill fractions (i.e. >; 60 vol%) reached with the proposed approach and to the reduction in the thermal resistance at contact locations by the silver necks. Furthermore, the present methodology is relatively insensitive to the shape and size of particles used, offering a great flexibility in material selection and quality (not acceptable for capillary-based underfills); and could enable efficient heat removal in future 3D chip stacks, flip-chip on board assemblies for mobile applications.

Enhanced Percolating Thermal Underfills Achieved by Means of Nanoparticle Bridging Necks

Efficient heat removal from integrated circuits arranged vertically in 3-D chip stacks requires thermally conductive underfill materials. The low-heat-transport performance of traditional capillary underfills can be improved by percolating the thermal conductive filler particles. We increased the thermal path by adding quasi-areal contacts using nanoparticle assemblies directed to the contact points of the percolating filler particles. We studied the formation and thermal effect of such nanoparticle neck assemblies in the filler-particle contact points using aqueous suspensions containing nanoparticles of different sizes, size distributions, and concentrations. An optimized binary mixture of small (28-43 nm) and large (200-300 nm) nanoparticles results in dense and defect-free neck assemblies. A neck-enhanced percolating thermal underfill (PTU) with a thermal conductivity as high as 2.4 W/mK was achieved using alumina filler and nanoparticles. Compared to a PTU, the addition of nanoparticle necks resulted in a more than twofold improvement in thermal conductivity.

All-Copper Flip Chip Interconnects by Pressureless and Low Temperature Nanoparticle Sintering

Flip chip interconnects purely made out of Cu, so-called all-Cu interconnects, have the potential to overcome the present current capacity limit of state-of-the-art solder based interconnects, while meeting the demand for ever decreasing interconnect pitches. Parasitic effects in solder based interconnects, caused by interdiffusion of various metals, are mitigated in all-Cu interconnects. In this work, all-Cu interconnects were formed by the use of low temperature and pressureless sintering of Cu nanoparticles. Thereby, a Cu paste material was applied between the Cu pillars of a silicon chip and the Cu pads on a silicon substrate by a dip transfer method. The electrical and mechanical properties of sintered Cu were characterized on films of the same Cu pastes. The porous films resulted in 4.4 times higher electrical resistivity and one order of magnitude reduced mechanical stiffness and tensile strength compared to bulk Cu. All-Cu interconnects with a diameter of 30 μm and a pitch of 100 μm were formed with an optimized Cu particle distribution and sintering procedure. Resistances down to 1.7 ± 0.5 mO were measured for these all-Cu interconnects which is comparable to solder based benchmark interconnects. However, the porosity of the sintered Cu interconnect results in lower shear strength compared to the solder benchmark.

Enhanced thermal underfills by bridging nanoparticle assemblies in percolating microparticle beds

A high thermally conductive underfill material is key for the efficient removal of heat generated by a 3-dimensional chip stack. Improved thermal properties are achieved by creating a percolating microparticle network within the composite underfill material. In this work, the directed assembly of nanoparticle necks formed by capillary bridging is investigated in order to improve the thermal transport in microparticle to microparticle contacts. The morphology of the formed necks using different alumina nanoparticle sizes and distributions, as well as a sol-gel binding system are characterized. High density and defect free nanoparticle necks were formed by using a mixture of small (28 - 43 nm) and large (200 - 300 nm) nanoparticles. The formation of such necks in the percolating alumina microparticle network increased the thermal conductivity of the underfill material from 1 W/mK without necks to 2.4 W/mK, a 2.4 × improvement in thermal conductivity.

Thermal characterization of percolating thermal underfills: Bulk and cavity

Three dimensional chip stacking benefits from thermally conductive intra-stack bondlines. Accurately determining the thermal conductivity of percolating thermal underfill (PTU) layers, made up of dielectric filler particles and epoxy, is challenging due to their reduced dimensions. The constrained dimensions may also influence the effective composite material properties. This study investigates how bulk samples compare to constrained cavity samples of identical material combinations, characterized by a steady state measurement technique. It is shown that the bulk thermal conductivity is reduced by over 35% in cavity layers. Reduced particle fill fractions at the chip interfaces due to cavity boundary effects which limit possible particle settling locations are the primary reason for this observation. Reduced dimensions in the size range of the filler particles consequently play a very significant role in effective medium properties of composite materials and need to be taken into account during material development.

Review of percolating and neck-based underfills with thermal conductivities up to 3 W/m-K

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-ofthe-art capillary thermal underfill (0.7 W/m-K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry vs. wet filling of filler particles, the optimal bi-modal nanosuspension formulation and matrix material feed, and the overpressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 500 thermal cycles. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-art capillary thermal underfill.

On the Evaporation of Colloidal Suspensions in Confined Pillar Arrays

The thermal and electrical transport capabilities of materials in electronic packaging are key to supporting high-performance microelectronic systems. In composite and hybrid materials, both of these transport capabilities are limited by contact resistances. We propose a directed nanoparticle assembly method to reduce contact resistances by transforming point contacts between micrometer-sized objects into quasi-areal contacts. The nanoparticle assembly is directed by the formation of liquid bridges in contact points during the evaporation of a colloidal suspension. In this work, we experimentally study the evaporation of colloidal suspensions in confined porous media to yield uniform nanoparticle assembly, as required for electronic packaging. The evaporation pattern of liquids in confined pillar arrays is either branched or straight, depending on the surface tension of the liquid and on the pore size defined by the pillar size and spacing. Stable evaporation fronts result in uniform nanoparticle deposition above a bond number threshold of 10