Severin Zimmermann

Significant thermal conductivity reduction of silicon nanowire forests through discrete surface doping of germanium

Silicon nanowires (SiNWs) are promising materials for the realization of highly-efficient and cost effective thermoelectric devices. Reduction of the thermal conductivity of such materials is a necessary and viable pathway to achieve sufficiently high thermoelectric efficiencies, which are inversely proportional to the thermal conductivity. In this article, vertically aligned forests of SiNW and germanium (Ge)-doped SiNW with diameters around 100 nm have been fabricated, and their thermal conductivity has been measured. The results show that discrete surface doping of Ge on SiNW arrays can lead to 23% reduction in thermal conductivity at room temperature compared to uncoated SiNWs. Such reduction can be further enhanced to 44% following a thermal annealing step. By analyzing the binding energy changes of Ge-3d and Si-2p using X-ray photoelectron spectroscopy, we demonstrate that surface doped Ge interacts strongly with Si, enhancing phonon scattering at the Si-Ge interface as has also been shown in non-equilibrium molecular dynamics studies of single nanowires. Overall, our results suggest a viable pathway to improve the energy conversion efficiency of nanowire-forest thermoelectric nanomaterials.

Waste heat recovery in supercomputers and 3D integrated liquid cooled electronics

Ever increasing device density in electronic chips is beneficial for enhancing their computing efficiency. However, it also introduces severe challenges with respect to cooling solution which are indispensible for ensuring a reliable chip operation. Such steady miniaturization will soon render the traditional air cooling strategies futile and make the switching to liquid cooling inevitable. Superior thermal properties and ubiquitous availability make water the most suitable candidate as coolant. Building up on the reported studies in the literature, which have already established the feasibility of water as coolant, here we show that the superior thermal properties of water make it possible to cool electronic chips and data centers using hot water with inlet temperature up to 60°C. The concept is demonstrated through measurements on a copper made scalable manifold microchannel heat sink and a hot water cooled data center prototype. The high exergetic efficiency achieved using hot water cooling should make it possible to reuse the heat otherwise discarded in data centers and therefore improve the overall system efficiency and lower the carbon foot print of the data centers. Finally, the encouraging results are used to model water cooling of 3D chip stacks using an interlayer integrated cooling approach. The model results are compared with measurements on a model simulator and good agreement is found, which lays the ground work for realizing a model based optimization of integrated cooling structures for 3D chip stacks.

Compact Thermal Model for the Transient Temperature Prediction of a Water-Cooled Microchip Module in Low Carbon Emission Computing

This article presents a compact computational model for the rapid determination of the junction temperature of a chip cooled with a heat sink, exploring the concept of hot water cooled electronics as a strategy to reduce the carbon footprint of data centers. The model aims at rapid simulations of variations of the chip, as well as the heat sink outlet water temperatures during transient heat loads. The model is validated by experimental tests with a water-cooled manifold microchannel (MMC) heat sink, which is designed to cool the processors of state-of-the-art servers. The chip temperature is determined subject to periodic heat loads as large as 100 W with frequencies in the range from 1 to 10 Hz. The results show that to calculate 1 s of real temperature variation requires less than 20 s of computational time on a Quad-Core AMD Opteron 2350, 2 GHz desktop PC with 4 GB RAM. The thermal response of the heat sink to real-time power traces with durations up to 200 s is modeled for different flow rates. The simulations indicate that application of a flow-control feedback loop could achieve more than 50% reduction in water flow rate, without compromising the maximal chip temperatures.

Enhanced Percolating Thermal Underfills Achieved by Means of Nanoparticle Bridging Necks

Efficient heat removal from integrated circuits arranged vertically in 3-D chip stacks requires thermally conductive underfill materials. The low-heat-transport performance of traditional capillary underfills can be improved by percolating the thermal conductive filler particles. We increased the thermal path by adding quasi-areal contacts using nanoparticle assemblies directed to the contact points of the percolating filler particles. We studied the formation and thermal effect of such nanoparticle neck assemblies in the filler-particle contact points using aqueous suspensions containing nanoparticles of different sizes, size distributions, and concentrations. An optimized binary mixture of small (28-43 nm) and large (200-300 nm) nanoparticles results in dense and defect-free neck assemblies. A neck-enhanced percolating thermal underfill (PTU) with a thermal conductivity as high as 2.4 W/mK was achieved using alumina filler and nanoparticles. Compared to a PTU, the addition of nanoparticle necks resulted in a more than twofold improvement in thermal conductivity.

Characterization of particle beds in percolating thermal underfills based on centrifugation

Heat dissipation in 3D chip stacks suffers from multiple thermal interfaces. The effective thermal resistance of the bond-line between individual dies, with the electrical interconnects can be minimized by the introduction of thermal conductive underfills. Up to now, only sequentially formed underfills result in true percolation and hence, thermal conductivities of more than 1 W/m-K. In this study, we report on various aspects to consider during the formation of percolating thermal underfills, by centrifugal filling of micron-sized particles and the subsequent backfilling of an epoxy by capillary action. Particle assemblies within silicon-glass cavities were investigated for mono and poly-dispersed spherical and facetted particles with characteristic dimension in the range of 15 μm to 50 μm. Clogging of particles between silicon pillars could be mitigated at low particle fluxes dispensed by the hour glass principle. Particle shadowing behind the silicon pillars could be eliminated by ultrasonic agitation. Finally, close to crystalline phases could be identified for the mono-dispersed particles, compared to a random packing for the poly-dispersed particles. The effective pore diameter of the particle beds was experimentally derived from a backfilling experiment with viscosity standards. A normalized pore diameter of 0.15, 0.17 to 0.20 and 0.11 was observed for mono and poly-dispersed spherical and facetted particles, respectively. The backfill dynamics can be predicted with those values and the Washburn equation. Cavities filled with particles down to 30 μm diameter could be filled completely with the available low viscosity epoxy system. Finally, we report on the re-arrangement of filler particles due to capillary action and viscous drag, during the backfilling process. Defects are minimal for fluids of low surface tension and high viscosity. Hence, only 1 area-% of defects were observed from the infiltration of epoxies.

Enhanced thermal underfills by bridging nanoparticle assemblies in percolating microparticle beds

A high thermally conductive underfill material is key for the efficient removal of heat generated by a 3-dimensional chip stack. Improved thermal properties are achieved by creating a percolating microparticle network within the composite underfill material. In this work, the directed assembly of nanoparticle necks formed by capillary bridging is investigated in order to improve the thermal transport in microparticle to microparticle contacts. The morphology of the formed necks using different alumina nanoparticle sizes and distributions, as well as a sol-gel binding system are characterized. High density and defect free nanoparticle necks were formed by using a mixture of small (28 - 43 nm) and large (200 - 300 nm) nanoparticles. The formation of such necks in the percolating alumina microparticle network increased the thermal conductivity of the underfill material from 1 W/mK without necks to 2.4 W/mK, a 2.4 × improvement in thermal conductivity.

Review of percolating and neck-based underfills with thermal conductivities up to 3 W/m-K

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-ofthe-art capillary thermal underfill (0.7 W/m-K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry vs. wet filling of filler particles, the optimal bi-modal nanosuspension formulation and matrix material feed, and the overpressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 500 thermal cycles. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-art capillary thermal underfill.

In Situ Assembly in Confined Spaces of Coated Particle Scaffolds as Thermal Underfills with Extraordinary Thermal Conductivity

In situ assembly of high thermal conductivity materials in severely confined spaces is an important problem bringing with it scientific challenges but also significant application relevance. Here we present a simple, affordable, and reproducible methodology for synthesizing such materials, composed of hierarchical diamond micro/nanoparticle scaffolds and an ethylenediamine coating. An important feature of the assembly process is the utilization of ethylenediamine as an immobilizing agent to secure the integrity of the microparticle scaffolds during and after each processing step. After other liquid components employed in the scaffolds assembly dry out, the immobilization agent solidifies forming a stable coated particle scaffold structure. Nanoparticles tend to concentrate in the shell and neck regions between adjacent microparticles. The interface between core and shell, along with the concentrated neck regions of nanoparticles, significantly enhance the thermal conductivity, making such materials an excellent candidate as thermal underfills in the electronics industry, where efficient heat removal is a major stumbling block toward increasing packing density. We show that the presented structures exhibit nearly 1 order of magnitude improvement in thermal conductivity, enhanced temperature uniformity, and reduced processing time compared to commercially available products for electronics cooling, which underpins their potential utility.

HOT WATER COOLED ELECTRONICS FOR HIGH EXERGETIC UTILITY

Cooling poses as a major challenge in the IT industry because recent trends have led to more compact and energy intensive microprocessors. Typically microprocessors in current consumer devices and state-of-the-art data centers are cooled using relatively bulky air cooled heat sinks. The large size heat sinks are required due to the poor thermophysical properties of air. In order to compensate for the poor thermal properties of air, it is typical to use chillers to pre-cool the air below the ambient temperature before feeding it to the heat sinks. Operating the chillers requires additional power input thereby making the cooling process more expensive. The growing cooling demand of electronic components will, however, render these cooling techniques insufficient. Direct application of liquid-cooling on chip level using directly attached manifold microchannel heat sinks reduces conductive and convective resistances, resulting in the reduction of the thermal gradient needed to remove heat. Water is an inexpensive, nontoxic and widely available liquid coolant. Therefore, switching from air to water as coolant enables a much higher coolant inlet temperature without in any way compromising the cooling performance. In addition, it eliminates the need for chillers and allows the thermal energy to be reused. All these improvements lead to higher thermal efficiency and open up the possibility to perform electronic cooling with higher exergetic efficiency. The current work explores this concept using measurements and exergetic analyses of a manifold microchannel heat sink and a small scale, first of its kind, hot water cooled data center prototype. Through the measurements on the heat sink, it is demonstrated that the heat load in the state-of-the-art microprocessor chips can be removed using hot water with inlet temperature of 60°C. Using hot water as coolant results in high coolant exergy content at the heat sink outlet. This facilitates recovering the energy typically wasted as heat in data centers, and can therefore result in data centers with minimal carbon footprint. The measurements on both the heat sink and the data center prototype strongly attest to this concept. Reuse strategies such as space heating and adsorption based refrigeration were tested as potential means to use the waste heat from data centers in different climates. Application-specific definitions of the value of waste heat were formulated as economic measures to evaluate potential benefits of various reuse strategies.Copyright