Jonathan B. Ashbrook
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Featured researches published by Jonathan B. Ashbrook.
IEEE Journal of Solid-state Circuits | 2006
Hyeon-Min Bae; Jonathan B. Ashbrook; Jinki Park; Naresh R. Shanbhag; Andrew C. Singer; Sanjiv Chopra
A maximum-likelihood sequence estimation (MLSE) receiver is fabricated to combat dispersion/intersymbol interference (chromatic and polarization mode), noise (optical and electrical), and nonlinearities (e.g., fiber, receiver photodiode, or laser) in OC-192 metro and long-haul links. The MLSE receiver includes a variable gain amplifier with 40-dB gain range and 7.5-GHz 3-dB bandwidth, a 12.5-Gb/s 4-bit analog-to-digital converter, a dispersion-tolerant phase-locked loop, a 1:8 demultiplexer, and a digital equalizer implementing the MLSE algorithm. The MLSE receiver achieves more than 50% reach extension at signal-to-noise levels of interest as compared to conventional clock data recovery systems
international solid-state circuits conference | 2006
Hyeon-Min Bae; Jonathan B. Ashbrook; Jinki Park; Naresh R. Shanbhag; Andrew C. Singer; Sanjiv Chopra
A 9.953 to 12.5Gb/s MLSE receiver consisting of an AFE IC in a 0.18mum 3.3V ft=75GHz, and a digital IC in a 0.13pm 1.2V CMOS is presented. The AFE IC features a 7.5GHz 40dB VGA, a 4b 12.5GS/S ADC, a dispersion-tolerant clock-recovery unit, and a 1:8 DEMUX. The digital IC implements an 8-parallel, delayed recursion MLSE architecture and a nonlinear channel estimator. The 4.5W receiver meets the SONET jitter specifications with 2200ps/nm of dispersion at BER=104
IEEE Journal of Solid-state Circuits | 2008
Hyeon-Min Bae; Jonathan B. Ashbrook; Naresh R. Shanbhag; Andrew C. Singer
This paper describes a fast power transient management functionality incorporated into a 12.5 Gb/s maximum likelihood sequence estimation (MLSE) receiver for optical add/drop multiplexer (OADM)-based WDM networks. The receiver has a VGA with a fast automatic gain control and a high-bandwidth offset cancellation loop. Measured results indicate that the receiver IC tolerates a 10 dB/10 mus optical power transient with 72 consecutive identical digits with no BER impact, and offers a 100 X improvement over a standard CDR in tracking an 8 dB sinusoidal power transient at a BER of 10-4 .
international solid-state circuits conference | 2008
Hyeon-Min Bae; Andrew C. Singer; Jonathan B. Ashbrook; Naresh R. Shanbhag
In this paper, a receiver IC is designed to recover data and clock in OC-192 OADM-based SONET WDM metro and long-haul networks. This is an electrical solution integrated into the receiver IC to address the power-transient problem for OC-192 links. An electrical solution reduces the cost and simplifies the operation. As power-transient management is added to an existing MLSE-based electronic dispersion compensation (EDC) receiver, in this paper, the focus is primarily on the blocks related to the power-transient management functionality. The MLSE receiver is implemented via an AFE IC in a 0.18 mum SiGe BiCMOS process, and a digital (MLSE equalizer) IC in a 0.13 mum 1.2 V CMOS process, with both dies packaged in a 23times17 mm2 261-pin multi-chip module (MCM).
Archive | 2007
Hyeon-Min Bae; Naresh R. Shanbhag; Jonathan B. Ashbrook
Archive | 2007
Hyeon-Min Bae; Naresh R. Shanbhag; Jonathan B. Ashbrook
Archive | 2008
Jonathan B. Ashbrook; Andrew C. Singer; Naresh R. Shanbhag; Robert J. Drost
Archive | 2007
Hyeon-Min Bae; Naresh R. Shanbhag; Jonathan B. Ashbrook
Archive | 2014
Jonathan B. Ashbrook; Nicholas F. Jungels
Archive | 2008
Heyon Min Bae; Naresh R. Shanbhag; Andrew C. Singer; Jonathan B. Ashbrook