Hyeon-Min Bae

An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links

A maximum-likelihood sequence estimation (MLSE) receiver is fabricated to combat dispersion/intersymbol interference (chromatic and polarization mode), noise (optical and electrical), and nonlinearities (e.g., fiber, receiver photodiode, or laser) in OC-192 metro and long-haul links. The MLSE receiver includes a variable gain amplifier with 40-dB gain range and 7.5-GHz 3-dB bandwidth, a 12.5-Gb/s 4-bit analog-to-digital converter, a dispersion-tolerant phase-locked loop, a 1:8 demultiplexer, and a digital equalizer implementing the MLSE algorithm. The MLSE receiver achieves more than 50% reach extension at signal-to-noise levels of interest as compared to conventional clock data recovery systems

Electronic dispersion compensation

This article provides an overview of some of the driving factors that limit the performance of optical links and highlight some of the potential opportunities for the signal processing community to make substantial contributions.

An MLSE receiver for electronic-dispersion compensation of OC-192 fiber links

A 9.953 to 12.5Gb/s MLSE receiver consisting of an AFE IC in a 0.18mum 3.3V ft=75GHz, and a digital IC in a 0.13pm 1.2V CMOS is presented. The AFE IC features a 7.5GHz 40dB VGA, a 4b 12.5GS/S ADC, a dispersion-tolerant clock-recovery unit, and a 1:8 DEMUX. The digital IC implements an 8-parallel, delayed recursion MLSE architecture and a nonlinear channel estimator. The 4.5W receiver meets the SONET jitter specifications with 2200ps/nm of dispersion at BER=104

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clock like periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mVppd to 1.06 Vppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 -12 is 42 mVppd. The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 -15 on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

Application of Kalman Gain for Minimum Mean-Squared Phase-Error Bound in Bang-Bang CDRs

This paper presents the minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking. An analogy between the Kalman filter and a linearized BB CDR is utilized for the derivation. The effects of demultiplexing, loop latency, and granular jitter are considered in the analysis to reflect reality. The validity of the theoretical analysis is supported by behavioral time domain simulation results.

Efficient Data Extraction Method for Near-Infrared Spectroscopy (NIRS) Systems With High Spatial and Temporal Resolution

An hardware-efficient method for the extraction of hemodynamic responses in near-infrared spectroscopy systems is proposed to increase the spatial and temporal resolution. The performance improvement is attributed to high signal-to-noise ratio receivers, a modulation scheme, and a multi-input-multi-output based data extraction algorithm. The proposed system shows more than twofold improvement in the figure of merit compared to conventional designs. Experimental results support the validity of the proposed system.

An efficient data extraction method for high-temporal-and-spatial-resolution near infrared spectroscopy (NIRS) systems

An efficient method for the extraction of hemodynamic response in near-infrared spectroscopy (NIRS) systems is proposed to increase the spatial and temporal resolution without hardware overhead. The performance improvement is attributed to high-signal-to-noise-ratio (SNR) receivers, a modulation scheme, and a multi input multi output (MIMO) based data extraction algorithm. The proposed systems shows a 72% increment in the figure of merit (FOM) compared to conventional designs. Experimental results support the validity of the proposed system.

11.1 A time-divided spread-spectrum code based 15pW-detectable multi-channel fNIRS IC for portable functional brain imaging

A custom transceiver IC is designed to implement a portable brain imaging system based on functional near-infrared spectroscopy (fNIRS). The fNIRS IC generates multichannel time-divided spread-spectrum codes (TDSSCs) and drives light-emitting devices in the transmitter (Tx) chain, and performs optimum filtering, quantization, and serialization in the receiver (Rx) chain. A dual slope ADC subsequent to an operational transconductance amplifier-C-based matched filter shares a capacitor to save area while achieving optimum signal-to-noise ratio (SNR) in the brain channel. The Rx chain including an off-chip TIA ensures sufficient electrical SNR irrespective of the brain region for the accurate extraction of hemodynamic response. The minimum detectable light power of the Rx chain is 400 fW. The output power of the Tx is made adjustable by controlling the occurrence rate and the power of the TDSSC to reduce subject-dependent measurement variations. The proposed fNIRS system measures 42 brain regions simultaneously, and the experimental results clearly verify the validity of the proposed portable fNIRS system.

A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links

This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 μm CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10-13 while consuming 82 mW at 10-Gb/s.