Jonathan B. Ballagh

Run-time reconfigurable 2D discrete wavelet transform using JBits

With the growth in high performance multimedia applications, specialized hardware for certain tasks is desirable. While ASICs provide a solution addressing performance, they are unable to provide an optimal solution for a given problem instance. FPGAs can be used with run-time reconfiguration to dynamically customize a circuit. Optimizations leading to faster circuits and reduced logic can result. The paper discusses the implementation of a run-time parameterizable 2D Discrete Wavelet Transform core using the JBits tool suite. The motivation for such a core is discussed, as well the benefits afforded by dynamic circuit specialization.

Specifying Control Logic for DSP Applications in FPGAs

New non-HDL programming models for signal processing in FPGAs have focused primarily on building high-performance data paths. Along with the ability to construct sophisticated custom signal processors comes increased requirements for creating complex control circuitry. Recent enhancements to System Generator for DSP begin to address this need by providing mechanisms that include co-simulation interfaces to extend Simulink with HDL semantics, automatic compilation from Matlab m-code into Simulink and VHDL, and embedded microcontrollers. In this paper, we describe how such mechanisms can be used in a QAM receiver designed for a CCSDS standard.