Nabeel Shirazi

Quantitative analysis of floating point arithmetic on FPGA based custom computing machines

Many algorithms rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Such computationally intensive algorithms are candidates for acceleration using custom computing machines (CCMs) being tailored for the application. Unfortunately, floating point operators require excessive area (or time) for conventional implementations. Instead, custom formats, derived for individual applications, are feasible on CCMs, and can be implemented on a fraction of a single FPGA. Using higher-level languages, like VHDL, facilitates the development of custom operators without significantly impacting operator performance or area. Properties, including area consumption and speed of working arithmetic operator units used in real-time applications, are discussed.

Compilation tools for run-time reconfigurable designs

This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: a partial evaluator, which produces configuration files for a given design, where the number of configurations can be minimised by a process, known as compile-time sequencing; an incremental configuration calculator, which takes the output of the partial evaluator and generates an initial configuration file and incremental configuration files that partially update preceding configurations; and a tool which further optimises designs for FPGAs supporting simultaneous configuration of multiple cells. While many of our techniques are independent of the design language and device used, our tools currently target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respect to its size to constant time at best and logarithmic time at worst.

Floating-point bitwidth analysis via automatic differentiation

Automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value in order to minimise the circuit area and to improve efficiency of the respective arithmetic operations, while satisfying user-defined numerical constraints. We present a novel approach to bitwidth- or precision-analysis for floating-point designs. The approach involves analysing the dataflow graph representation of a design to see how sensitive the output of a node is to changes in the outputs of other nodes: higher sensitivity requires higher precision and hence more output bits. We automate such sensitivity analysis by a mathematical method called automatic differentiation, which involves differentiating variables in a design with respect to other variables. We illustrate our approach by optimising the bitwidth for two examples, a discrete Fourier transform (DFT) implementation and a Finite Impulse Response (FIR) filter implementation.

Automating production of run-time reconfigurable designs

This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit configurations are matched to locate the components common to them, so that reconfiguration time can be minimized. The circuit configurations are represented as a weighted bipartite graph, to which an efficient matching algorithm is applied. Our method, which supports hierarchical and library-based design, is device-independent and has been tested using Xilinx 6200 FPGAs. A number of examples in arithmetic, pattern matching and image processing are selected to illustrate our approach.

System Level Tools for DSP in FPGAs

Visual data flow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally specified by signal flow graphs. Although several academic and commercial frameworks provide a high level of abstraction for modeling DSP systems, they have drawbacks as design tools for FPGAs. They do not provide efficient implementations, and their system behavior only approximates the hardware implementation. In this paper, we describe a software system that employs a visual data flow environment for system modeling and algorithm exploration. In this environment, the bit and cycle behavior of the FPGA implementation are manifest. By observing circuit behavior in the system environment, one obtains significant speed improvement over hardware simulation, while gaining substantial flexibility afforded by functional abstraction. In addition, the software automatically generates a faithful hardware implementation from the system model. Specific issues addressed include the mapping of system parameters into implementation (e.g., sample rates, enables), and implications of system modeling for testing (e.g., testbench generation).

Quantitative Analysis of FPGA-based Database Searching

This paper reports two contributions to the theory and practice of using reconfigurable hardware to implement search engines based on hashing techniques. The first contribution concerns technology-independent optimisations involving run-time reconfiguration of the hash functions; a quantitative framework is developed for estimating design trade-offs, such as the amount of temporary storage versus reconfiguration time. The second contribution concerns methods for optimising implementations in Xilinx FPGA technology, which achieve different trade-offs in cell utilisation, reconfiguration time and critical path delay; quantitative analysis of these trade-offs are provided.

Pipeline morphing and virtual pipelines

Pipeline morphing is a simple but effective technique for reconfiguring pipelined FPGA designs at run time. By overlapping computation and reconfiguration, the latency associated with emptying and refilling a pipeline can be avoided. We show how morphing can be applied to linear and mesh pipelines at both word-level and bit-level, and explain how this method can be implemented using Xilinx 6200 FPGAs. We also present an approach using morphing to map a large virtual pipeline onto a small physical pipeline, and the trade-offs involved are discussed.

Automating Customisation of Floating-Point Designs

This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of re-configurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost functionn with a given error specification for the output relative to a reference representation can be satisfied. We adopt an iterative implementation of this method, which supports IEEE single-precision or double-precision floating-point representation as the reference representation. This implementation produces customised floating-point formats with arbitrary-sized mantissa and exponent. The tool follows a generic framework designed to cover a variety of arithmetic representations and their hardware implementations; both combinational and pipelined designs can be developed. Results show that, particularly for calculations involving large dynamic ranges, our tool can produce hardware that is smaller and faster when compared with a design adopting the reference representation.

A framework for developing parametrised FPGA libraries

We suggest that the productivity of FPGA users can be improved by adopting design libraries which are optimally implemented, rich in variety, easy to use, compatible with incremental development techniques and carefully validated. These requirements motivate our research into a framework for developing FPGA libraries involving the industrial-standard VHDL language and the declarative language Ruby. This paper describes the main elements in our framework, and illustrates its application to the Xilinx 6200 series FPGAs.

Run-Time Management of Dynamically Recongigurable Designs

A method for managing reconfigurable designs, which supports run-time configuration transformation, is proposed. This method involves structuring the reconfiguration manager into three components: a monitor, a loader, and a configuration store. Various trade-offs can be achieved in reconfiguration time, the optimality of the reconfigured circuits, and the complexity of the reconfiguration manager. We consider methods of reconfiguration and ways of exploiting run-time information available at compile time, and study their impact on design trade-offs. The proposed techniques, implementable in hardware or software, are supported by our tools and can be applied to both partially and non-partially reconfigurable devices. We describe the combined and the partitioned reconfiguration methods, and use them to illustrate the techniques and the associated trade-offs.