Jonathan Wu

A Novel Economical Embedded Multi-mode Intelligent Control System for Powered Wheelchair

In order to assist different kinds of disabled persons and senior citizens, to lower the cost and improve the effectiveness and convenience of human-machine interaction, a novel economical embedded multi-mode intelligent control system for powered wheelchair is developed. The system is based on a high-performance 16-bit compact single chip system. It has “Manual”, “Speech”, “Vision”, and “Autonomous” four modes that are fulfilled by four modules. The mode and the corresponding module can be customized according to the needs of different users and situations and that makes a further lower cost. In addition, fusion of multi-mode and other security measures are discussed. The hardware, software, control mechanism, and some experimental results are elaborated in the paper.

Moving object segmentation using the 9/7–10/8 dual-tree complex filter bank

This paper introduces our recently designed 9/7-10/8 dual-tree complex filter bank and studies its application in moving object detection and segmentation. The dual-tree complex wavelet transform (DT-CWT) is used in edge detection required for segmentation in video frames. The DT-CWT approach is compared with the previous methods based on scalar wavelets and multi-wavelets (MW), using double change detection (DCD) technique. The results show that DT-CWT with the 9/7-10/8 filter bank compare favorably to the previous results in terms of the number of detected edges and the correctness of the segmented area.

Competitive Learning Techniques for Color Image Segmentation

A method for color image segmentation using a competitive learning clustering scheme is examined, and some basic improvements are made. Two important aspects of the color image segmentation problem, namely color space selection and oversegmentation, are discussed in the context of the algorithm, with comments about suitability and effectivenessof choices for various applications. A variety of settings are tested and compared to highlight performance.

Low power high performance keeper technique for high fan-in dynamic gates

This paper presents a new technique which combines Variable-Threshold (VT) keeper with Split-Domino (SD) logic technique to improve the power performance. The proposed technique yields 9-14% energy reduction, with 10% area overhead. We will compare the proposed method with the-state-of-the art for reducing leakage current in domino logic circuits. A 16-bit multiplexer circuit, in 0.13μm CMOS technology operating at 500 MHz is used as our test-bench.

Complexity reduced mode selection of H.264/AVC intra coding

One of the new features in the H.264/AVC encoder is the use of Lagrangian rate-distortion optimization (RDO) method during mode decision at the macroblock level. The RDO technique has been employed in H.264/AVC for intra prediction mode selection to achieve better coding efficiency. But the computation complexity of mode decision algorithm is extremely high. To reduce the complexity of mode decision, we propose an efficient and fast 4 times 4 intra prediction mode selection scheme. The proposed method reduces the candidate of the prediction modes based on the sum of absolute transformed difference (SATD) between the original block and the intra predicted block. Rank of each mode is obtained based on the SATD value. The candidate modes are further reduced by using the combination of rank and most probable mode. Simulation results demonstrate that the proposed mode decision method reduces about 95% of mode decision time of intra coding with ignorable degradation of coding performance.

Efficient mixed-signal synapse multipliers for multi-layer feed-forward neural networks

An area and power-efficient modular mixed-signal synapse architecture is proposed for VLSI implementation of the multi-layer feed-forward neural network. The proposed circuitry multiplies synaptic weights that are stored in digital registers with the analog input. The multiplication result is always an analog current. Despite conventional MDACs principle in which all the multiplication work is performed based on weighted current mirrors, our structure performs the multiplication partially by small-area gates. This approach decreases the need for weighted current mirrors and lowers the size of transistors significantly. Modularity feature of the proposed circuit in combination with the scalable S-shaped neuron makes the structure capable of being easily adapted for various network configurations. This feature and the area-efficient multiplier design make the circuit an excellent choice to be used in large size multi-layer neural networks. The circuit is implemented in TSMC CMOS 0.18μm. The power at the maximum input level is 244um2. The area is 0.23mW with the measured output current error of less than 0.5μA.

A survey on leakage control techniques in wide-OR domino circuits

In this paper, we compare different existing keeper techniques for reducing power consumption of wide domino logic circuits. We will compare power consumption plus area overhead of each of these methods, with the conventional keeper circuit. A 16-bit multiplexer circuit, in 0.13µm CMOS technology operating at a frequency of 500 MHz is our test-bench. Simulations show Split-Domino (SD), with 53% less power consumption, and 10.5% more area, has the best performance.