Mitra Mirhassani

Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function

Nonlinear activation function is one of the main building blocks of artificial neural networks. Hyperbolic tangent and sigmoid are the most used nonlinear activation functions. Accurate implementation of these transfer functions in digital networks faces certain challenges. In this paper, an efficient approximation scheme for hyperbolic tangent function is proposed. The approximation is based on a mathematical analysis considering the maximum allowable error as design parameter. Hardware implementation of the proposed approximation scheme is presented, which shows that the proposed structure compares favorably with previous architectures in terms of area and delay. The proposed structure requires less output bits for the same maximum allowable error when compared to the state-of-the-art. The number of output bits of the activation function determines the bit width of multipliers and adders in the network. Therefore, the proposed activation function results in reduction in area, delay, and power in VLSI implementation of artificial neural networks with hyperbolic tangent activation function.

Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron

An important part of any hardware implementation of artificial neural networks (ANNs) is realization of the activation function which serves as the output stage of each layer. In this work, a new NMOS/PMOS design is proposed for realizing the sigmoid function as the activation function. Transistors in the proposed neuron are biased using only one biasing voltage. By operating in both triode and saturation regions, the proposed neuron can provide an accurate approximation of the sigmoid function. The neuron circuit is designed and laid out in 90-nm CMOS technology. The proposed neuron can be potentially used in implementation of both analog and hybrid ANNs.

Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing

In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-mum technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250mum2.

Digital Multiplication using Continuous Valued Digits

Binary multiplication is one of the fundamental arithmetic operations, and it is used in digital filters and signal processing applications. The continuous valued number system (CVNS) is a recently introduced number system that allows digital arithmetic, with arbitrary precision, to be implemented with analog circuitry. Due to the analog nature of the numbers system, CVNS reduces the total system and cross talk noise. An 8 times 8 digital multiplier is proposed, using CVNS compressors for reducing the digital partial products. A new definition for the CVNS compressor for the first time is introduced, along with a novel CMOS current mode circuit. The multiplier is realized in TSMC CMOS 0.18mum technology, with a maximum delay of 900ps, static power consumption of 19mW and a core area of 11200 mum2. The example demonstrates that CVNS designs can yield fast, low power arithmetic circuits using low noise analog circuitry.

Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio

Resistive-type distributed neural networks (DNNs) provide a self-scaling structure for the neuron, which can spontaneously adapt itself to different numbers of inputs. In lumped neural networks, the neuron should be changed whenever the number of inputs changes due to the applications; redesigning the neuron is not practical, particularly for hardware implementations. In this brief, a group of feedforward DNNs based on a continuous valued number system is proposed, which outperforms not only the lumped neural networks but also the conventional DNNs because of the reduced sensitivity to noise.

An area-speed efficient method for current mode analog to digital converters

A novel method for converting analog information to digital in current mode is proposed. This configuration is efficient in terms of speed and area consumption. It is designed for a 4-bit conversion in particular, although it can be easily expanded for more number of bits. For a 4-bit approach, the proposed Analog to Digital Conversion Method (ADCM) provides the conversion of each two bits at the same time resulting in a fast conversion. In addition, its specific architecture occupies a small area. The proposed ADCM is suitable for current mode applications.

CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory

Multi-valued dynamic memories are appropriate for applications such as implementation of neural networks, where massive number of synaptic weights have to be stored on a chip. In this paper, a novel storage and refreshing configuration to store up to 4 bits (16 levels) per cell on a dynamic memory is proposed. This configuration is based on the Continuous Valued Number System (CVNS). Error correction method according to the CVNS properties is used in order to increase the noise margin of memory cells. Furthermore, by decreasing the leakage current, the refresh cycle time is increased. The circuits are designed, simulated, and finally laid out using 90-nm CMOS technology.

On control of HCCI combustion-neural network approach

Due to environmental consideration and recent regulations on the car emission, new technologies are explored. HCCI engine, thanks to its low NOx emission and high efficiency may be one of the candidate solutions. Therefore, exploration of enhanced HCCI combustion control is of strong interest to both the auto industry and the academic community and of a challenge due to complexities in ignition timing prediction. In this paper, application of a neural network assisted controller for a control-based model of an HCCI combustion engines is explore. The model is updated on-line and is used to predict the ignition timing. Simulation results show that the controller is able to predict the proper inputs to the model and to track the desired peak pressure accurately. Hence a neural-network-based control strategy could be potentially established for HCCI combustion control

16-bit radix-4 continuous valued digit adder

The Continuous Valued Number System (CVNS) is a novel analog digit number system which employs bit level analog residue arithmetic. The information redundancy among the digits, makes it easy to perform the required binary operations in higher radices, and reduces the implementation area and the number of required interconnections. CVNS theory can open up a new approach for performing digital arithmetic with simple and elementary analog elements, such as current comparators and current mirrors, and with arbitrary precision. In this paper we discuss the design of 16-bit radix-4 CVNS adder with controlled precision, and a two operand binary adder designed, in TSMC CMOS 0.18μm technology, is used to illustrate the techniques.

16-bit Binary Multiplication Using High Radix Analog Digits

In this paper, a binary multiplier based on the Continuous Valued Number System (CVNS), and consisting of arrays of current mode modulo adders, is discussed. The Continuous Valued Number System uses analog current mode circuitry, with attendant very low system noise, to create arithmetic units with arbitrary equivalent digital precision. A series of analog digits, computing over arbitrary radix rings is used, in a forward correction mode, to achieve this comparable digital accuracy despite the fact that the implementation employs only relatively simple analog circuits. To reduce the area and power requirements in CVNS multipliers, columns of partial products are added in higher radices. In this paper, details of the design and implementation of a 16-bit binary multiplier in radix-4 CVNS are provided.