Jong-Ee Oh

A Hardware Efficient LDPC Encoding Scheme for Exploiting Decoder Structure and Resources

Previously, there has been no report on implementation effort to integrate LDPC encoder and decoder into a single hardware. In this paper, we propose a simple yet low complex systematic LDPC encoding method for class of quasi-cyclic low-density parity-check (QC-LDPC) codes to let LDPC encoder acquire an interchangeable structure, exploited in the decoder. With the proposed encoding scheme, implementation of the proposed encoder becomes much more hardware efficient than having a separate hardware due to LDPC encoder and decoder resource sharing. Moreover, the overall computational complexity of the proposed encoding scheme is lower than the well-known Richardsons efficient encoding scheme (A.T.J. Richardson and R.L. Urbanke, 2001).

Row-Splitting Design of Low-Density Parity-Check Codes for Gbps Transmission

In this paper, we propose a design methodology of low-density parity check (LDPC) code for very high speed transmission. To support various code rates with reasonable hardware and, possibly, the type-II hybrid automatic repeat request (HARQ), a row-splitting/combining method is employed in conjunction with shortening. In row-splitting approach, a parity check matrix of a high rate mother LDPC code, saying rate 5/6, is designed first and then successively row-split the mother matrix to obtain lower rate codes. Shortening provides us another degree of freedom for rate and frame length flexibility for concatenation with MIMO system. The code performance is investigated in terms of frame error rate and compared with those of the LDPC code proposed in IEEE 802.16e standard.

Row-splitting design of Low-Density Parity-Check Codes for Gbps wireless transmission

In this paper, we propose a design methodology of low-density parity check (LDPC) code for very high speed wireless transmission. To support various code rates with reasonable hardware a row-splitting/combining method is employed in conjunction with shortening. In row-splitting approach, a parity check matrix of a high rate mother LDPC code, saying rate 4/5, is designed first and then successively row-split the mother matrix to obtain lower rate codes. Shortening provides us another degree of freedom for rate and frame length flexibility for concatenation with MIMO system. The code performance is investigated in terms of frame error rate and compared with those of the LDPC code proposed in IEEE 802.16e standard.