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Dive into the research topics where Jong-heun Lim is active.

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Featured researches published by Jong-heun Lim.


international interconnect technology conference | 2016

450mm Cu single damascene BEOL process with 20nm half-pitched features

Sun-OO Kim; Shannon Dunn; Steven Smith; WenLi Collision; Jamie Prudhomme; Huey-Ming Wang; Joe Maniscalco; Nithin Yathapu; Chulgi Song; Barry Wang; Christopher R. Carr; Hsi-Wen Liu; Bruce Gall; Angelo Alaestante; Min-Hui Chen; Richard Conti; ChungJu Yang; Denis Sullivan; Kosta Culafi; BumKi Moon; Yii-Cheng Lin; Yu-Lieh Fu; Katherine Sieg; Anne-Sophie Larrea; Norman Fish; Regina Swaine; Alexander Bialy; Milo Tallon; Gerard Stapf; John Hagwood

At 450mm wafer area, the first Cu BEOL module process was demonstrated with a single damascene structure using low-k ILD, TiN metal hard mask and guided 20nm half-pitched lamella BCP DSA patterning. It showed the potential opportunities, technical feasibility and further challenges for coming needs for 450mm equipment.


advanced semiconductor manufacturing conference | 2016

STI 28nm pitch guided DSA to enable the 450mm tools qualification and transition

Anne-Sophie Larrea; Shannon Dunn; Wenli Collison; Daniel Franca; Christopher L. Borst; Janghee Lee; Jong-heun Lim; Stock Chang

One of the options to reduce the cost related to the next generation of devices in the semiconductor industry is the scale up of the wafer size from 300mm to 450mm. The 450mm transition requires the development and qualification of new tools and processes. G450C, a partnership between five international integrated circuit (IC) makers and CNSE (College of Nanoscale Science and Engineering), has been created to lead this transition. Patterned wafers are necessary to test and demonstrate these 450mm tools. The challenge has been to develop and validate a patterning process — capable of producing advanced-node-relevant features — in a timely manner to enable the process and tool demonstrations. Based on the provided and available 450mm processes and tools, a 28nm pitch STI (Shallow Trench Isolation) structure on a 450mm wafer was developed. This feature was made possible using a 193nm immersion lithography DSA (Directed Self Assembly) technique. This paper will update G450C program status and show process results obtained on 450mm wafers using an STI structure.


Archive | 2011

Methods of manufacturing three-dimensional semiconductor devices

Hyu-Jung Kim; Sang-Yong Park; Jong-heun Lim; Kyung-Hyun Kim; Chang-Sup Mun


Archive | 2008

Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods

Suk-Hun Choi; In-Gyu Baek; Seong-Kyu Yun; Jong-heun Lim; Chagn-Ki Hong; Bo-Un Yoon


Archive | 2012

MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES

Hyo-Jung Kim; Daehong Eom; Jong-heun Lim; Myung-Jung Pyo; Byoung-moon Yoon; Kyung-Hyun Kim


Archive | 2005

Chemical mechanical polishing (CMP) slurries and CMP methods using and making the same

Jong-heun Lim; Jae-dong Lee; Bo-Un Yoon; Chang-Ki Hong


Archive | 2007

METHOD OF MANUFACTURING A STACK-TYPE SEMICONDUCTOR DEVICE

Sang-Yeob Han; Chang-Ki Hong; Bo-Un Yoon; Young-Ho Koh; Seong-Kyu Yun; Jong-heun Lim


Archive | 2012

Non-volatile memory device including etch stop layer pattern

Jong-heun Lim; Ki-ho Bae; Hyo-Jung Kim; Kyung-hyun Kim; Chan-wook Seo; Youngbeom Pyon


Archive | 2008

Apparatus for polishing a wafer and method for detecting a polishing end point by the same

Jong-heun Lim; Sung-Ho Shin; Bo-Un Yoon; Chang-ki Hong


Archive | 2013

CHEMICAL MECHANICAL POLISHING MACHINE AND POLISHING HEAD ASSEMBLY

In-Kwon Kim; Kyung-hyun Kim; Ki-Jong Park; Ki-ho Bae; Jong-heun Lim

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