Chang-ki Hong

Control of Microscratches in Chemical-Mechanical Polishing Process for Shallow Trench Isolation

A method of controlling microscratches on silicon oxide surfaces induced by chemical-mechanical polishing (CMP) process for the planarization of shallow trench isolation is discussed. The frequency of microscratches during polishing shows its high dependency on the characteristics of CMP consumables such as slurry and pad. A diluted slurry solution, pH-controlled with a potassium hydroxide (KOH) solution of pH 13, produces best results in reducing microscratches on silicon oxide surfaces during polishing. In conclusion, careful preparation of the CMP consumables is required to reduce microscratches on silicon oxide during polishing.

The Effect of Pad Properties on Planarity in a CMP Process

This study presents the effect of pad properties, such as elastic modulus and surface roughness, on planarity in a CMP process. A systematic method to measure planarization length , which represents the die-scale planarity in a quantitative manner, has been proposed. It has been shown that the planarization length is highly dependent on the bulk modulus of the pad. The effect of elastic modulus and roughness of the pad on dishing amount, which represents the feature-scale planarity, has been shown. Dishing amount is determined by the elastic modulus of the superficial layer of the pad, which is typically tens of microns thick, rather than by the bulk elastic modulus of the pad. A double layer pad model has been proposed based on the observed results, which can explain that the dishing amount is reduced by increasing elastic modulus of the pad superficial layer, or by decreasing the surface roughness of the pad.

Effect of Ashing, Strip and Annealing Process on the Dopant Concentration of Silicon

Introduction Silicon has been used successfully for semiconductor material because it can have a high degree of purity at a low cost, and shows the good mechanical, chemical and electrical properties. In the respect of electrical properties, the pure silicon is an insulator, thus the ion implantation process is necessary to make insulating silicon into semiconductor. Generally, the electrical properties of silicon based semiconductors are determined by the characteristics of dopant. Hence the study for the change of dopants concentration in following process such as ashing, strip, and annealing, is very important. (Shown in Figure 1.) In this study, we will discuss about the loss of dopant by strip process using fluorine-based stripper and annealing.

Effect of Wettability of Poly Silicon on CMP Behavior

The hydrophobicity of poly Si is reported to introduce different polishing behavior with careful control of post CMP cleaning process. The purpose of this study was to investigate the effect of poly Si wettability on its CMP behavior. The adhesion force of polymeric particle on the poly Si wafer surfaces was measured in the KOH solution (pH 11) as a function of solution A concentration. Adhesion force decreased and saturated as a function of concentration of solution A. The change of surface wettability affects not only the polishing rates but also the level of contamination on wafer because the interactions between particles and substrates are dependent on the wettability of the surface. Also, hydrophobic poly Si surfaces attracted much more pad particles with water marks than hydrophilic

Effect of Silicon Dioxide Hardness on Scratches in Interlevel Dielectric Chemical–Mechanical Polishing

In the silicon dioxide chemical–mechanical polishing (CMP) process, one of the most challenging issues is the formation of defects such as scratches. In this study, scratch formation behavior and CMP performance were evaluated on high-density plasma oxide (HDP), plasma-enhanced tetraethylorthosilicate (PETEOS), and borophosphosilicate glass (BPSG) wafers. To evaluate the number of scratches after the CMP process, contaminated abrasive particles were removed using an optimized post-CMP cleaning process consisting of scrubber cleaning and dilute SC1 megasonic cleaning. The oxide wafers were then treated with dilute hydrogen fluoride (HF) in order to improve the visibility of the generated scratches. The number and shape of the scratches were investigated as a function of oxide film hardness. The results show that a decrease in film hardness correlates with an increase in the number of scratches. Three different types of scratches (chatter marks, line, and rolling) were observed on the oxide surfaces. The dominant scratch shape on all three oxide films was chatter mark–type scratches. This could be attributed to the stick–slip phenomenon. However, the overall fraction of chatter marks compared to other types of scratches (especially line scratches) was proportional to the film hardness. It was also found that scratch depth was strongly influenced by the polishing pressure during CMP. The results clearly show that the mechanical pro- perties of the surface play a critical role in scratch generation.