Jong Ok Ha

A 54–862-MHz CMOS Transceiver for TV-Band White-Space Device Applications

A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional-N synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single-conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as well as the harmonic mixing problem in the receiver. A fractional-N phase-locked loop (PLL) with only a single LC VCO and a wideband multimodulus local oscillator (LO) generator seamlessly covers the entire band. A wideband semi-dynamic divide-by-1.5 circuit is adopted in the LO generator to reduce the VCO tuning range requirement by 25 %. A pseudoexponential capacitor bank structure in the LC VCO substantially reduces the KVCO and fstep variations across the total band, which is beneficial for maintaining the PLL loop stability and dynamics over the wide band. The transceiver is implemented in 0.18-μ m CMOS, and operates with a single 1.8-V supply. The transmitter delivers a nominal output power of -3 dBm, and exhibits OP1 dB of >; +6.4 dBm, OIP3 of >; +15.9 dBm, and error vector magnitude (EVM) of <; -34.7 dB for 64-QAM signal. The image and carrier leakage calibration circuits suppress the leakage components below -41 dBc across the entire band. The receiver achieves about 100-dB gain dynamic range, 3.5-6.9-dB noise figure, <; -29-dB EVM, and -43.4/-59.7-dBc third/fifth harmonic mixing suppression. The synthesizer and LO generator achieves the integrated phase noise <; 0.8 rms degree over the entire band.

A 54–862 MHz CMOS direct conversion transceiver for IEEE 802.22 cognitive radio applications

A CMOS single-chip transceiver IC is developed for IEEE 802.22 cognitive radio applications. Over the 54 to 862 MHz ultra wideband, the in-band harmonic distortions of the transmitter and the unwanted harmonic mixing of the receiver are effectively suppressed by exploiting the dual-path direct-conversion architecture. A seamless coverage of the full band is achieved by employing a fractional-N PLL with a single LC VCO and a multi-modulus LO generator. Implemented in 0.18 µm CMOS, the receiver achieves 110 dB gain dynamic range, ≪ 8.5 dB noise figure, and ≫ −11 dBm IIP3 at the LNA bypass mode. The transmitter delivers −3 dBm output power with OP1dB and OIP3 greater than +6.4 dBm and +15.9 dBm, respectively. On-chip calibration circuits suppress the image and carrier leakage components below −41 dBc across the total band.

A fully integrated 3–5 GHz UWB RF transceiver for WBAN applications

A fully integrated 3-5 GHz CMOS UWB RF transceiver for wireless body area network (WBAN) is presented with the textile antenna in this paper. To achieve the low power and low complexity, OOK receiver topology and the digitally synthesized impulse generator are employed. For the rejection of the undesired interferers below 2.4 GHz, the tunable RF notch filter is integrated and the measured sensitivity shows 10 dB improvement of the sensitivity coexistent with the -30 dBm / 2.4 GHz interference. The transmitted UWB signal is generated in digital circuits, and both of the carrier frequency and bandwidth can be tunable. The measured energy efficiency of transmitter and the receiver sensitivity are 20.6 pJ/bit and -65 dBm, respectively. The measured maximum distance of communication is 1.5 m with the textile antenna in LOS channel.

A precisely gain controlled RF front end for T-DMB tuner ICs

A precisely gain controlled RF front end is developed for T-DMB tuner IC applications. A precise RF gain control with 50dB dynamic range is achieved in RF VGA by employing a capacitive ladder type attenuator. The proposed method enables us to design and analyze very fine gain step VGA concretely. Implemented in 0.13µm CMOS, the tuner RF front end consumes 9.7mA at 1.2V supply. Measured results are NF < 1.5dB at the maximum gain and the accurate 1dB gain step is obtained.

A 3-5GHz IR-UWB CMOS RF transceiver with RF notch filter

A fully integrated 3 ~ 5GHz CMOS RF transceiver for IR-UWB applications is implemented in 0.18 m CMOS technology. The integrated RF notch filter is employed to reject the nearby WiFi and WCDMA interferers. The low power digital impulse generator is used as the UWB RF transmitter. The measured sensitivity of the receiver is 65 dBm at 4GHz with 1Mbps PRF. And the measured energy efficiency per pulse is 20.6 pJ/bit. The current consumption of the receiver and transmitter including DA is 27.5mA and 25.5mA, respectively, at 1.8V supply.

A CMOS mobile TV tuner with precise RF gain control and fast locking PLL for multiband FM/T-DMB/DAB applications

A fully integrated tuner IC based on low-IF architecture is developed for triple-band FM/T-DMB/DAB applications. A precise RF gain control with 50 dB dynamic range is achieved in RF VGA by employing a capacitive ladder type attenuator. A novel coarse tuning scheme based on a RF frequency-to-digital converter allows fast and agile automatic VCO frequency calibration, leading to fast locking in PLL. Implemented in 0.13 µm CMOS, the tuner consumes 57 mA from 1.2 V supply. Measured results are NF &#60; 1.5 dB at the maximum gain and IIP3 > 0 dBm with LNA bypassed. The integrated phase noise of ΔΣ fractional-N PLL is less than 1 rms degree, and the coarse tuning time is less than 2.03 µsec.

A 3~5 GHz Interferer Robust IR-UWB RF Transceiver for Data Communication and RTLS Applications

This paper presents a IR-UWB(Impulse Radio Ultra-Wide Band) transceiver circuit for data communication and real time location system. The UWB receiver is designed to OOK(On-Off Keying) modulation for energy detection. The UWB pulse generator is designed by digital logic. And the Gaussian filter is adopted to reject side lobe in transmitter. The measured sensitivity of the receiver is —65 dBm at 4 GHz with 1 Mbps PRF(Pulse Repetition Frequency). And the measured energy efficiency per pulse is 20.6 pJ/bit. The current consumption of the receiver and transmitter including DA is 27.5 mA and 25.5 mA, respectively, at 1.8 V supply.

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

A 3-5 GHz UWB radar chip in 0.13 ㎛ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.