Jong-Uk Bae

New Depletion-Mode IGZO TFT Shift Register

A new shift register employing bottom-gate In-Ga-Zn-O thin-film transistors (IGZO TFTs) was proposed and fabricated. Depletion-mode IGZO TFTs were successfully turned off by employing two low-voltage-level signals. The IGZO shift register exhibited a high-voltage output pulse without any distortion and a maximum clock frequency of 417 kHz. The proposed shift register would be an important building block for a depletion-mode oxide TFT display.

Competitive device performance of low-temperature and all-solution-processed metal-oxide thin-film transistors

In this Letter, we described a solution-processed indium-gallium-zinc oxide thin-film transistors (TFTs) with a solution-processed aluminum oxide phosphate gate dielectric, fabricated at a maximum annealing temperature under 350 °C to be applicable to conventional fabrication process of flat-panel displays (FPDs). The solution-processed TFTs exhibited competitive device characteristics under 350 °C, including a field-effect mobility of 4.50 cm2/Vs, an on-to-off current ratio of ∼109, a threshold voltage of 2.34 V, and a subthreshold gate swing of 0.46 V/dec, making them applicable to the future backplane of FPDs.

Origin of the improved mobility and photo-bias stability in a double-channel metal oxide transistor.

This study examined the performance and photo-bias stability of double-channel ZnSnO/InZnO (ZTO/IZO) thin-film transistors. The field-effect mobility (μFE) and photo-bias stability of the double-channel device were improved by increasing the thickness of the front IZO film (t(int)) compared to the single-ZTO-channel device. A high-mobility (approximately 32.3 cm(2)/Vs) ZTO/IZO transistor with excellent photo-bias stability was obtained from Sn doping of the front IZO layer. First-principles calculations revealed an increase in the formation energy of O vacancy defects in the Sn-doped IZO layer compared to the IZO layer. This observation suggests that the superior photo-bias stability of the double-channel device is due to the effect of Sn doping during thermal annealing. However, these improvements were observed only when t(int) was less than the critical thickness. The rationale for this observation is also discussed based on the oxygen vacancy defect model.

The effects of buffer layers on the performance and stability of flexible InGaZnO thin film transistors on polyimide substrates

We demonstrated the fabrication of flexible amorphous indium gallium zinc oxide thin-film transistors (TFTs) on high-temperature polyimide (PI) substrates, which were debonded from the carrier glass after TFT fabrication. The application of appropriate buffer layers on the PI substrates affected the TFT performance and stability. The adoption of the SiNx/AlOx buffer layers as water and hydrogen diffusion barriers significantly improved the device performance and stability against the thermal annealing and negative bias stress, compared to single SiNx or SiOx buffer layers. The substrates could be bent down to a radius of curvature of 15 mm and the devices remained normally functional.

Formation of CoTi barrier and increased thermal stability of CoSi2 film in Ti capped Co/Si(100) system

We investigated the formation of CoSi2 for Ti capped Co on (100) Si substrate with emphasis on the Co–Ti interaction and its effect on thermal stability. A 15 nm thick Ti capping layer is shown to improve the interfacial roughness and thermal stability of CoSi2 film grown on Si substrate compared with TiN capping. The increased uniformity of silicide/Si(100) interface is speculated to result from retarded Co–Si reaction by the formation of CoTi binary phase. And the high thermal stability can be explained by the fact that the amount of Ti atoms in CoSi2 film for Ti capping is much higher than what is in TiN capping. It is likely that the surface Ti diffuses rapidly into CoSi2 grain boundaries and slows down the agglomeration process, thereby increasing thermal stability while Ti in TiN capping did not.

High thermal stability and low junction leakage current of Ti capped Co salicide and its feasibility for high thermal budget CMOS devices

A thermally stable cobalt salicide has been fabricated using Ti-capping Co/Si system. A Ti-capping layer is shown to improve the interfacial roughness and thermal stability of CoSi/sub 2/ film grown on Si substrate comparing with TiN-capping. It is attributed to high amount of Ti atoms in Co disilicide film, which slow down the agglomeration. According to the results of salicided gate and junction, Ti capped CoSi, had stable characteristics when the thermal budget increased up to 850/spl deg/C for 90 min. Therefore, Ti-capping Co salicide structure can be acceptable to fabricate DRAM and LOGIC-embedded DRAMs.

Single-Scan Monochromatic Photonic Capacitance-Voltage Technique for Extraction of Subgap DOS Over the Bandgap in Amorphous Semiconductor TFTs

We report a novel technique for simultaneous extraction of subgap donor- and acceptor-like density of states [g_D(E) and g_A(E)] over the subgap energy range (E_V <;E<;E_C) using a single-scan monochromatic photonic capacitance-voltage technique in n-channel amorphous indium-gallium-zinc-oxide thin-film transistors. In the proposed technique, we applied two different equivalent circuit models for the photoresponsive carriers excited from g_D(E) and g_A(E) under depletion (V_GS <; V_FB) and accumulation (V_GS <; V_FB) bias by employing a sub-bandgap optical source that includes a relation between photon energy (E_ph) and bandgap energy (E_g) as h_v = E_ph <; E_g.

76.2: Development of Highly Stable a‐IGZO TFT with TiOx as a Passivation Layer for Active‐Matrix Display

Titanium oxide (TiOx) was employed for passivation layer of indium-gallium-zinc oxide (a-IGZO) TFTs. Molybdenum (Mo) and titanium (Ti) was used as a source-drain metal. It is demonstrated the titanium layer could be used as an etch stopper layer to protect the back channel of a-IGZO during Mo etching process and transformed into TiOx by the surface treatment using oxygen plasma. From device measurement, we have observed that Ion/Ioff ratio and mobility are ∼108 and 9 cm2 V−1 sec−1, respectively. AMLCD panel has been demonstrated to verify the device uniformity and performance.

9.3: Control of Threshold Voltage in Back Channel Etch Type Amorphous Indium Gallium Zinc Oxide Thin Film Transistors

Tuning the process pressure at the deposition of the passivation layers has been suggested in the way of controlling the threshold voltage of a-IGZO TFTs, making it possible to employ gate driver integration. It has showed that Vth linearly changes with the pressure ΔVth/ΔPressure∼3.5V/100Pa. A 3.2 inch WVGA AMLCD with integrated gate driver circuits were successfully demonstrated using the enhancement mode BCE type bottom gate a-IGZO TFTs.

Extraction Technique for Intrinsic Subgap DOS in a-IGZO TFTs by De-Embedding the Parasitic Capacitance Through the Photonic

We report a technique for extraction of the intrinsic subgap density of states (gA,int(E)) by deembedding the parasitic capacitance in amorphous indium-gallium-zinc-oxide TFTs through the optical charge pumping method. As structure-dependent parameters in the proposed extraction technique, the overlap length L_OV between the source/drain (S/D) and the active layer and the parasitic overlap area between the gate and the S/D metal (C_par,S/C_par,D) are considered under dark and subbandgap photonic states. We obtained g_A,int(E) as a superposition of the exponential deep and tail states with N_TA,int = 6.0 × 10¹⁶ eV^-1·cm^-3, kTT_A,int = 0.16 eV,N_DA,int = 1.8 × 10¹⁵ eV^-1 · cm^-3, and kT_DA,int = 1.9 eV from samples with various parasitic areas.