Binn Kim

Highly Reliable Depletion-Mode a-IGZO TFT Gate Driver Circuits for High-Frequency Display Applications Under Light Illumination

We proposed and fabricated a depletion-mode amorphous indium-gallium-zinc-oxide thin-film transistor gate driver without any additional signals. The proposed gate driver successfully exhibited a high-voltage output pulse without distortion at a clock frequency of 100 kHz, which is enough to drive a high-frequency panel with a frame rate of ~360 Hz and a resolution of full high definition. The experimental and simulation results showed that the gate driver would be highly reliable under light illumination. Also, the output waveform of the gate driver was not distorted after 240-h driving under 450-nm illumination with an intensity of 1 mW/ cm2 at 60°C.

A Novel Depletion-Mode a-IGZO TFT Shift Register With a Node-Shared Structure

We proposed and fabricated a new depletion-mode amorphous indium-gallium-zinc-oxide thin-film-transistor (TFT) shift register with a node-shared structure. The proposed shift register requires 14 TFTs, 3 clock lines, and 3 power source lines for two output pulses, whereas the previous shift registers consisted of more than 22 TFTs, 4 clock lines, and 6 power source lines. The experimental results showed that the proposed shift register successfully generated two output pulses at one stage without any distortion. The circuit area of the proposed shift register is reduced by about 30%, as compared with that of the previous one.

P-18: Highly Stable a-Si TFT Gate Driver with Simple Logic Circuit

A novel integrated gate driver with a simple logic circuit (SLC) using 5 a-Si TFTs has been developed. The noise voltage owing to clock coupling is eliminated effectively with an overlapped clock controlled transistor. The SLC gate driver, successfully integrated in 14.1-in. XGA TFT-LCDs, shows marked stability despite the extremely simple structure.

P‐3: Scaling of a‐Si TFT Gate Drivers

The characteristic feature of an optimum design of a-Si gate driver circuits and its scaling properties are presented. The delay time of the output pulse of gate driver circuits with different layout characteristics was analyzed by a distributed-load modeling. The effect of TFT properties, clock phase and the output load on the optimum condition is given. Finally, scaling has been found to give apparent power law dependence on the circuit area, signifying higher performance of the circuits with smaller area.