Jong-Yeol Park | Researchain

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international solid-state circuits conference | 2012

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

Dae-Yeal Lee; Ik Joon Chang; Sangyong Yoon; Joon-Suc Jang; Dong-Su Jang; Wook-ghee Hahn; Jong-Yeol Park; Doo-gon Kim; Chi-Weon Yoon; Bong-Soon Lim; Byung-Jun Min; Sung-Won Yun; Ji-Sang Lee; Il-Han Park; K. Kim; Jeong-Yun Yun; Y. Kim; Yongsung Cho; Kyung-Min Kang; Sang-Hyun Joo; Jin-Young Chun; Jung-No Im; Seunghyuk Kwon; Seokjun Ham; An-Soo Park; Jae-Duk Yu; Nam-Hee Lee; Taesung Lee; Moosung Kim; Hoo-Sung Kim

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

international solid-state circuits conference | 2016

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

Seung-Jae Lee; Jin-Yub Lee; Il-Han Park; Jong-Yeol Park; Sung-Won Yun; Min-Su Kim; Jong-Hoon Lee; Minseok S. Kim; Kangbin Lee; Tae-eun Kim; ByungKyu Cho; Dooho Cho; Sangbum Yun; Jung-No Im; Hyejin Yim; Kyung-Hwa Kang; Suchang Jeon; Sungkyu Jo; Yang-Lo Ahn; Sung-Min Joe; S. Kim; Deok-kyun Woo; Jiyoon Park; Hyun Wook Park; Young-Min Kim; Jonghoon Park; Yongsu Choi; Makoto Hirano; Jeong-Don Ihm; Byung-Hoon Jeong

NAND flash memory is widely used as a cost-effective storage with high performance [1-2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640μs program time and a 800MB/s I/O rate is achieved.

Archive | 2005