Jongkil Park

A 65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver

We present a 65k-neuron integrate-and-fire array transceiver (IFAT) for spike-based neural computation with low-power, high-throughput connectivity. The internally analog, externally digital chip is fabricated on a 4×4 mm2 die in 90 nm CMOS and arranged in 4 quadrants of 16k parallel addressable neurons. Each neuron circuit serves input spike events by dynamically instantiating conductance-based synapses onto four local synapse circuits over two membrane compartments, and produces output spike events upon reaching a threshold in integration over one of the membrane compartments. Fully asynchronous input and output spike event data streams are mediated over the standard address event representation (AER) protocol. To support full event throughput at large synaptic fan-in, a two-tier micro-pipelining scheme parallelizes input events along neural array cores, and along rows of each core. Measured results show sustained peak synaptic event throughput of 18.2 Mevents/s per quadrant, at 22 pJ average energy per synaptic input event and 25 μW standby power.

Scalable event routing in hierarchical neural array architecture with global synaptic connectivity

An asynchronous communication scheme for scalable routing of spike events in large-scale neuromorphic hardware is presented. The routing scheme extends the Address-Event Representation (AER) protocol for spike event communication to a modular, hierarchical architecture supporting efficient implementation of global synaptic inter-connectivity across a cellular matrix of message parsing axonal relay nodes at varying spatial scales. This paper presents a probabilistic framework for analyzing trade-offs in throughput and latency of synaptic communication as a function of load and geometry, and simulation results verifying the statistics of traffic flow across the architecture.

Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is the real-time synaptic routing in a large-scale spiking neuron architecture. Here we present a hierarchical address-event routing (HiAER) communication architecture for routing neural events in a scaleable reconfigurable large-scale neuromorphic system. The neural events are routed in real-time through synaptic connections with configurable parameters governing connectivity, synaptic strength, and axonal delay. The HiAER architecture is implemented on a hardware platform with five Xilinx Spartan-6 FPGA cores.

85 dB dynamic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible active electrode array

We present the design, implementation, and experimental characterization of a low-noise low-power biopotential recording integrated circuit (IC) in support of a fully implantable, high-density, actively multiplexed and flexible 32×32 electrode array for electrocorticography (ECoG) neural recording. Each ECoG recording IC contains an 8-channel ADC, each serving one column and multiplexing up to 32 rows in the external ECoG array. Each column ADC converts signal coarsely by 10-bit successive approximation (SA), and performs fine conversion of the residue by 7-bit 1st order incremental delta-sigma (ΔΣ) conversion. One bit of overlap between SA and ΔΣ stages supports wide dynamic range with an instantaneous core range of 3.9 mV, sufficiently larger than typical ECoG signals, while handling electrochemical and process variations in the ECoG electrode array up to ±1 V. Tests show a measured dynamic range of 85 dB and CMRR of 87 dB at 19.5 kS/s and at 19.4 μA from 3.3 V per ADC channel. The 8-channel IC occupies 18 mm2 in 0.6 μm 2P3M CMOS.

Improved contrast sensitivity DVS and its application to event-driven stereo vision

This paper presents a new DVS sensor with one order of magnitude improved contrast sensitivity over previous reported DVSs. This sensor has been applied to a bio-inspired event-based binocular system that performs 3D event-driven reconstruction of a scene. Events from two DVS sensors are matched by using precise timing information of their ocurrence. To improve matching reliability, satisfaction of epipolar geometry constraint is required, and simultaneously available information on the orientation is used as an additional matching constraint.

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at

Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link

3.6\times 10^{7}

Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link

synaptic events per second per 16k-neuron node in the hierarchy.

Event-driven neural integration and synchronicity in analog VLSI

We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.

A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation

We present a telemetry IC with a new data modulation scheme for efficient simultaneous transfer of power and backward data over a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive energy while inducing an instantaneous voltage change on the primary side. Contrary to conventional load shift keying modulation, the recovery time of the secondary LC oscillation after shorting improves asymptotically with increasing quality factor of the secondary LC tank. Since quality factor does not reduce the data rate, the LC tank can be simultaneously optimized for power and data telemetry, obviating the conventional tradeoff between power transfer efficiency and data rate. Cyclic ON-OFF keying time-encoded symbol data mapping of the shorting cycle allows transmission of two data bits per four carrier cycles while supporting simultaneous power delivery during at least six nonshorting out of eight half cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and a phased-locked loop. The 0.92 mm2 65 nm CMOS IC delivers up to 11.5 mW power to the load and simultaneously transmits 6.78 Mb/s data while dissipating 64 μW power. A bit error rate of ≤9.9 × 10-8 was measured over a single 1 cm 13.56 MHz inductive link at a data rate of 6.78 Mb/s with a 10 mW load power.