Sohmyung Ha

Integrated Circuits and Electrode Interfaces for Noninvasive Physiological Monitoring

This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

A 65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver

We present a 65k-neuron integrate-and-fire array transceiver (IFAT) for spike-based neural computation with low-power, high-throughput connectivity. The internally analog, externally digital chip is fabricated on a 4×4 mm2 die in 90 nm CMOS and arranged in 4 quadrants of 16k parallel addressable neurons. Each neuron circuit serves input spike events by dynamically instantiating conductance-based synapses onto four local synapse circuits over two membrane compartments, and produces output spike events upon reaching a threshold in integration over one of the membrane compartments. Fully asynchronous input and output spike event data streams are mediated over the standard address event representation (AER) protocol. To support full event throughput at large synaptic fan-in, a two-tier micro-pipelining scheme parallelizes input events along neural array cores, and along rows of each core. Measured results show sustained peak synaptic event throughput of 18.2 Mevents/s per quadrant, at 22 pJ average energy per synaptic input event and 25 μW standby power.

85 dB dynamic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible active electrode array

We present the design, implementation, and experimental characterization of a low-noise low-power biopotential recording integrated circuit (IC) in support of a fully implantable, high-density, actively multiplexed and flexible 32×32 electrode array for electrocorticography (ECoG) neural recording. Each ECoG recording IC contains an 8-channel ADC, each serving one column and multiplexing up to 32 rows in the external ECoG array. Each column ADC converts signal coarsely by 10-bit successive approximation (SA), and performs fine conversion of the residue by 7-bit 1st order incremental delta-sigma (ΔΣ) conversion. One bit of overlap between SA and ΔΣ stages supports wide dynamic range with an instantaneous core range of 3.9 mV, sufficiently larger than typical ECoG signals, while handling electrochemical and process variations in the ECoG electrode array up to ±1 V. Tests show a measured dynamic range of 85 dB and CMRR of 87 dB at 19.5 kS/s and at 19.4 μA from 3.3 V per ADC channel. The 8-channel IC occupies 18 mm2 in 0.6 μm 2P3M CMOS.

Silicon-Integrated High-Density Electrocortical Interfaces

Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.

A 144MHz integrated resonant regulating rectifier with hybrid pulse modulation

This paper presents a CMOS fully-integrated resonant regulating rectifier (IR³) for inductive power telemetry in implantable devices. Employing PWM and PFM feedback, the IR³ achieves 1.87% of ΔV_DD/V_DD ratio despite a tenfold change in load with a 1nF decoupling capacitor. At 1V regulation of a 100μW load from a 144MHz RF input, the measured voltage conversion efficiency is greater than 92% at under 5.2mV_pp ripple and 54% power conversion efficiency. Implemented in 180nm SOI CMOS, the IR³ circuit occupies 0.078mm² active area.

Towards high-resolution retinal prostheses with direct optical addressing and inductive telemetry.

OBJECTIVE Despite considerable advances in retinal prostheses over the last two decades, the resolution of restored vision has remained severely limited, well below the 20/200 acuity threshold of blindness. Towards drastic improvements in spatial resolution, we present a scalable architecture for retinal prostheses in which each stimulation electrode is directly activated by incident light and powered by a common voltage pulse transferred over a single wireless inductive link. APPROACH The hybrid optical addressability and electronic powering scheme provides separate spatial and temporal control over stimulation, and further provides optoelectronic gain for substantially lower light intensity thresholds than other optically addressed retinal prostheses using passive microphotodiode arrays. The architecture permits the use of high-density electrode arrays with ultra-high photosensitive silicon nanowires, obviating the need for excessive wiring and high-throughput data telemetry. Instead, the single inductive link drives the entire array of electrodes through two wires and provides external control over waveform parameters for common voltage stimulation. MAIN RESULTS A complete system comprising inductive telemetry link, stimulation pulse demodulator, charge-balancing series capacitor, and nanowire-based electrode device is integrated and validated ex vivo on rat retina tissue. SIGNIFICANCE Measurements demonstrate control over retinal neural activity both by light and electrical bias, validating the feasibility of the proposed architecture and its system components as an important first step towards a high-resolution optically addressed retinal prosthesis.

A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation

A four-channel multi-input multi-output (MIMO) complex baseband receiver for spectrum and space-aware cognitive radio applications is presented. The MIMO baseband receiver comprises a capacitive harmonic-rejection downconverting mixer (HRM) receiver and a signal-separation multi-input multi-output analog core (MAC) on a single integrated circuit. The HRM receiver performs frequency selection of the incoming RF signals by programmable spectral downconversion and filtering with minimal harmonic folding. The subsequent MAC separates the spectrally overlapping but spatially diverse signals by weighted complex matrix multiplication. The entire signal path is implemented using energy-efficient gm-C analog circuits with digitally controlled capacitive weighting for configurable baseband down-/upconversion ranging from -24 to +24 MHz in the HRM, and programmable spatial filtering with 4×4 complex (8×8 real) 14-bit coefficients in the MAC. Measurements demonstrate greater than 65 dB harmonic-folding rejection by the HRM, and greater than 48.5 dB spatial signal separation by the MAC. The 65 nm CMOS IC occupies 3.27 mm2 active area, and consumes 480 μW digital power at 45 MHz LO and 840 μW analog power at 3 MHz baseband from a 1.2 V supply.

Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process

This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical NPN transistor (V-NPN) as a tail current source in a 0.18-/spl mu/m CMOS process. V-NPN has an inherently low flicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-NPN are measured and extracted for design convenience. The proposed VCO that used a V-NPN current source instead of nMOS is verified using a 0.18-/spl mu/m deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 /spl mu/W from the 1.8-V supply.

A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distribution

An adaptive buck-boost resonant regulating rectifier (B²R³) with an integrated on-chip coil and low-loss H-Tree power/signal distribution is presented for efficient and robust wireless power transfer (WPT) over a wide range of input and load conditions. The B²R³ integrated on a 9 mm² chip powers integrated neural interfacing circuits as a load, with a TX-load power conversion efficiency of 2.64 % at 10 mm distance, resulting in a WPT system efficiency FoM of 102.

Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link

We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.