Jongmin Lee

Block recycling schemes and their cost-based optimization in nand flash memory based storage system

Flash memory has many merits such as light weight, shock resistance, and low power consumption, but also has limitations like the erase-before-write property. To overcome such limitations and to use it efficiently as storage media in mobile systems, Flash memory based storage systems require special address mapping software called the FTL (Flash-memory Translation Layer). Like cleaning in Log-structured file system (LFS), the FTL often performs a merge operation for block recycling and its efficiency affects the performance of the storage system. To reduce the block recycling costs in NAND Flash memory based storage, we introduce another block recycling scheme that we call migration. Our cost-models and experimental results show that cost-based selection of merge or migration for each block recycling can decrease block recycling costs and, therefore, improve performance of Flash memory based storage systems. Also, we derive the macroscopic optimal migration/merge sequence minimizing block recycling costs for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be further improved by the macroscopic optimization than the simple cost-based selection.

Improving SSD reliability with RAID via Elastic Striping and Anywhere Parity

While the move from SLC to MLC/TLC flash memory technology is increasing SSD capacity at lower cost, it is being done at the cost of sacrificing reliability. An approach to remedy this loss is to employ the RAID architecture with the chips that comprise SSDs. However, using the traditional RAID approach may result in negative effects as the total number of writes may increase due to the parity updates, consequently leading to increased P/E cycles and higher bit error rates. Using a technique that we call Elastic Striping and Anywhere Parity (eSAP), we develop eSAP-RAID, a RAID scheme that significantly reduces parity writes while providing reliability better than RAID-5. We derive performance and lifetime models of SSDs employing RAID-5 and eSAP-RAID that show the benefits of eSAP-RAID. We also implement these schemes in SSDs using DiskSim with SSD Extension and validate the models using realistic workloads. Our results show that eSAP-RAID improves reliability considerably, while limiting its wear. Specifically, the expected lifetime of eSAP-RAID employing SSDs may be as long as current ECC based SSDs, while its reliability level can be maintained at the level of the early stages of current ECC based SSDs throughout its entire lifetime.

CPS-SIM: configurable and accurate clock precision solid state drive simulator

NAND flash memory is the most widely used storage medium in embedded systems today due to its many advantages such as light weight, low power consumption, and shock resistance. Recently, solid state drives (SSDs), which use NAND flash memory to store data, are replacing conventional magnetic disks in laptops and some server computers. In the SSDs, to achieve both high performance and large capacity, a number of flash memory chips are connected to multiple buses and SSD firmware exploits parallel accesses by using interleaving and overlapping techniques. However, it is still unclear how many buses or chips should be used and how to drive those chips and buses to satisfy performance that may be required. To help answer these questions, we have developed a clock precision SSD simulator (CPS-SIM) that simulates the internal behavior of an SSD and that reports timing and utilization information. From the accurate timing and utilization results of CPS-SIM, we can discover the optimal hardware configuration including the number of buses and chips and their interconnections in an SSD. Also, it allows for fast development and verification of SSD firmware that runs an FTL (Flash Translation Layer) optimized for an SSD. Unlike FTLs for embedded flash memory, the FTL for an SSD must utilize the concurrency of the multiple chips and buses. By supporting concurrency, our CPS-SIM provides a flexible environment for design of SSD firmware that drives the multiple flash memory chips and also that schedules data transmissions via the multiple buses.

Enhancing SSD reliability through efficient RAID support

A serious problem with current SSDs is its low reliability due to their primary component, flash-memory, that has high error rate and limited erase count. Adopting RAID architecture is a reasonable way to increase reliability of SSDs. In this paper, we propose Dynamic and Variable Size Striping-RAID (DVS-RAID) that dynamically constructs a variable size stripe based on arrival order of write requests such that write requests are sequentially written to a stripe improving the performance and lifetime of SSDs. To increase the reliability of small writes without making use of non-volatile RAM, DVS-RAID employs variable size striping, which constructs a new stripe with data written to portions of a full stripe and writes a parity for that partial stripe. We implement DVS-RAID in the DiskSim SSD extension, and experimental results based on trace-driven simulations show that DVS-RAID outperforms the conventional RAID-5 scheme in terms of performance and lifetime of SSDs.

TinyFTL: an FTL architecture for flash memory cards with scarce resources

In this paper, we focus on firmware design for flash memory cards that have scarce resources such as small amount of SRAM and low performance processors. Our design goals include devising practical, commercial grade features required for commercial flash memory cards and minimizing memory requirements to support these features. To this end, we propose TinyFTL (Flash Translation Layer) that has low memory requirements for implementing full features such as efficient garbage collection, mapping, caching, and fast boot-up. Through implementation and experiments, we show that even with smaller memory footprints TinyFTL performs better in terms of performance and boot-up time than implementations of state-of-the-art FTLs.

Real-time flash memory storage with Janus-FTL

Janus-FTL, a recently proposed Flash Translation Layer (FTL) software layer for flash memory storage, has the potential to reduce the worst case write time of flash memory storage by keeping hot data in the page mapping area and cold data in the block mapping area. In this paper, we present the design of the real-time Janus-FTL that guarantees worst case garbage collection cost and write response time. In the proposed FTL, each task needs to decide whether to place its data either in the page mapping area or the block mapping area. A naive optimal placement algorithm, which minimizes the worst case write time, has O(2N) time complexity for N tasks. We propose an algorithm reducing the time complexity from O(2N) to O(N log N). Through experiments, we verify that the real-time Janus-FTL reduces the worst case write time and, as a result, accommodates more real-time tasks than the previous state-of-the-art realtime page mapping FTL.